Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising:

• a substrate including a cell area and a peripheral circuit area;
• first and second transistors each including a gate electrode, a source region, and a drain region, formed on the substrate;
• a first interlevel dielectric layer formed over an entire surface of the substrate including the first and second transistors, and having a bit line contact hole and a lower electrode contact hole formed in the cell area and a metal wiring contact hole formed in the peripheral circuit area;
• a bit line connector formed within the bit line contact hole of the first interlevel dielectric layer and electrically connected to the drain region of the first transistor;
• a bit line formed on the interlevel dielectric layer and electrically connected to the bit line connector;
• a bit line capping pattern covering the bit line;
• a capacitor lower electrode connector, formed within the lower electrode contact hole of the first interlevel dielectric layer, that extends to a same level as the bit line capping pattern;
• a capacitor formed on the capacitor lower electrode connector, the capacitor including a lower electrode, a dielectric layer and an upper electrode;
• and
• a lower metal wiring contact plug formed within the metal wiring contact hole and connected to the drain region or the gate electrode of the second transistor.

A method of manufacturing a semiconductor memory device comprising:

• preparing a substrate;
• forming transistors on the substrate, each transistor having a gate electrode structure including a gate electrode, a gate electrode capping pattern formed on the gate electrode, and sidewall spacers formed on sidewalls of the gate electrode and the gate electrode capping pattern, and having a source region and a drain region;
• forming a first interlevel dielectric layer including a bit line contact hole, over an entire surface of the substrate including the transistors and which has high selectivity with respect to the gate electrode capping pattern and the sidewall spacers;
• forming a bit line connector electrically connected to a drain region of at least one of the transistors, by filling the bit line contact hole with a conductive material;
• forming a bit line on the first interlevel dielectric layer including the bit line connector;
• forming a bit line capping pattern covering the bit line;
• forming a second interlevel dielectric layer, having high selectivity with respect to the gate electrode capping pattern and the sidewall spacers, over an entire surface of the first interlevel dielectric layer including the bit line capping pattern;
• forming a mask pattern on the second interlevel dielectric layer which exposes a portion of the second interlevel dielectric layer corresponding to a source region of at least one of the transistors and which extends along a direction of the bit line;
• etching the first and second interlevel dielectric layers using the mask pattern to form a capacitor lower electrode contact hole exposing the source region of the at least one of the transistors;
• filling the capacitor lower electrode contact hole from a bottom thereof up to a top surface of the bit line capping pattern with the conductive material, to form a capacitor lower electrode connector positioned at a same level as the bit line capping pattern;
• and
• forming a capacitor on the capacitor lower electrode connector, the capacitor including a lower electrode, a dielectric layer, and an upper electrode.

A method of manufacturing a semiconductor memory device comprising:

• preparing a substrate including a cell area and a peripheral circuit area;
• forming transistors on the substrate including the cell area and the peripheral circuit area, each transistor having a gate electrode structure including a gate electrode, a gate electrode capping pattern formed on the gate electrode, and sidewall spacers formed at sidewalls of the gate electrode and the gate electrode capping pattern, and having a source region and a drain region;
• forming a first interlevel dielectric layer over an entire surface of the substrate including the transistors;
• etching the first interlevel dielectric layer to simultaneously form a bit line contact hole in the cell area and a metal wiring contact hole in the peripheral circuit area;
• and
• filling the bit line contact hole and the metal wiring contact hole with a conductive material, to simultaneously form a bit line connector connected to a drain region of at least one of the transistors formed in the cell area and a metal contact connector connected to a drain region or a gate electrode of at least one of the transistors formed in the peripheral circuit area.