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US 2003/0151081 A1Published application
Memory cell capacitors having an over/under configuration
AssigneeMicron Technology, Inc.
InventorFernando Gonzalez
Life of this patent
Estimating the term…
Abstract
Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.
Claims31
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a capacitor below a channel region of the access transistor, wherein the capacitor is coupled to the first source/drain region of the access transistor;
- wherein the capacitor is overlying at least a portion of a capacitor of a second memory cell;
- and
- wherein the second memory cell has an access transistor having a source/drain region coupled to the bit line.
3 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a capacitor coupled to the first source/drain region of the access transistor through an extension;
- wherein the extension is laterally adjacent a second capacitor of a second memory cell;
- and
- wherein the capacitor of the memory cell is underlying at least a portion of the second capacitor of the second memory cell.
3 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a first cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a second cell capacitor having a storage node laterally adjacent the extension of the first memory cell.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell;
- and
- wherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell.
2 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein the first memory cell further includes a first cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a second cell capacitor having a storage node laterally adjacent the extension of the first memory cell.
5 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell.
5 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell;
- and
- wherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell.
5 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a container capacitor coupled to the first source/drain region of the access transistor;
- wherein the container capacitor is overlying at least a portion of a container capacitor of a second memory cell;
- and
- wherein the second memory cell has an access transistor having a source/drain region coupled to the bit line.
3 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a container capacitor coupled to the first source/drain region of the access transistor through an extension;
- wherein the extension is laterally adjacent a second container capacitor of a second memory cell;
- and
- wherein the container capacitor of the memory cell is underlying at least a portion of the second container capacitor of the second memory cell.
3 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a first cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor;
- and
- wherein the second memory cell further includes a second cell capacitor at least a portion of which is below the first cell capacitor.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor;
- and
- wherein the second memory cell further includes a cell capacitor interposed between a channel region of the second access transistor and the cell capacitor of the first memory cell.
2 more elements
Dependencies are inferred from the claim text.