US 2003/0151069 A1 · Semiconductor device and manufacturing method

Abstract

A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

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Claims29

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate;
a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other;
a second diffusion region formed adjacent to and apart from an end of the plurality of first diffusion regions formed substantially in line on the semiconductor substrate;
a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions and the second diffusion region;
a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode;
a first insulation film filled between adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes and the selection gate electrode, formed at a substantially uniform thickness on a side surface of the peripheral gate electrode, and including a main component other than nitrogen;
and
a second insulation film formed on at least the side surface of the peripheral gate electrode via the first insulation film and formed of a material different from that of the first insulation film.

6 more elements

A semiconductor device, comprising:

a semiconductor substrate;
a first and a second memory cell array disposed on the semiconductor substrate, each of the first and the second memory cell array comprising:
a plurality of memory cell transistors each having a memory cell gate and source/drain diffusion regions, the memory cell transistors being disposed adjacent to one another sharing one of the source/drain diffusion regions and being connected in series;
and
selection transistors formed on the semiconductor substrate at opposite ends of the plurality of memory cell transistors connected in series, sharing one of the source/drain diffusion regions with the memory cell transistors of the opposite ends, and having a first diffusion region disposed on the semiconductor substrate as the other of the source/drain diffusion regions,
one of the selection transistors of the first memory cell array being disposed adjacent to one of the selection transistors of the second memory cell array to share the first diffusion region;
a peripheral circuit portion disposed apart from the first and the second memory cell array and having a peripheral transistor formed on the semiconductor substrate, the peripheral transistor including a peripheral gate electrode;
a first insulation film filled between adjacent ones of the plurality of memory cell transistors, formed at a substantially uniform thickness on a side surface of the peripheral gate electrode so as to set a thickness between the memory cell gates to be larger than the substantially uniform thickness on the side surface of the peripheral electrode, formed at a substantially zero thickness on a surface of the semiconductor substrate on opposite sides of the peripheral gate electrode, and including a main component other than nitrogen;
and
a second insulation film formed on at least the side surface of the peripheral gate electrode via the first insulation film.

7 more elements

A manufacturing method of a semiconductor device, comprising:

forming a first gate electrode layer, a first insulation film, and a second gate electrode layer on a semiconductor substrate in this order;
by processing the second gate electrode layer, the first insulation film, and the first gate electrode layer by lithography, forming a plurality of memory cell gate electrodes in a memory cell portion, while simultaneously forming a peripheral gate electrode in a peripheral circuit portion;
by using the plurality of memory cell gate electrodes and the peripheral gate electrode as masks, forming a plurality of diffusion regions on the semiconductor substrate;
forming a second insulation film so as to fill between adjacent ones of the plurality of memory cell gate electrodes and cover the memory cell gate electrodes of the memory cell portion entirely and continuously, while simultaneously forming the second insulation film along a side surface of the peripheral gate electrode of the peripheral circuit portion and along the semiconductor substrate adjacent to an underpart of the peripheral gate electrode, and
removing the second insulating film formed on the semiconductor substrate adjacent to the underpart of the peripheral gate electrode.

2 more elements

A manufacturing method of a semiconductor device, comprising:

forming a first memory cell gate array including a plurality of memory cell gate electrodes, a first selection gate pair formed on opposite ends of the first memory cell gate array, a second memory cell gate array including a plurality of memory cell gate electrodes, and a second selection gate pair formed on opposite ends of the second memory cell gate array such that one gate of the second selection gate pair is disposed adjacent to one gate of the first selection gate pair, while forming a plurality of peripheral gates apart from the first memory cell gate array, the first selection gate pair, the second memory cell gate array, and the second selection gate pair on a semiconductor substrate;
by using the first memory cell gate array, the first selection gate pair, the second memory cell gate array, the second selection gate pair, and the plurality of peripheral gates as masks, forming a plurality of diffusion regions in the semiconductor substrate;
forming a first insulation film including a main component other than nitrogen over a whole surface of the semiconductor substrate, so as to fill between adjacent ones of the plurality of memory cell gate electrodes, between the opposite ends of the first memory cell gate array and the first selection gate pair, and between the opposite ends of the second memory cell gate array and the second selection gate pair, and to form the first insulation film on a side surface of one gate of the first selection gate pair disposed adjacent to and opposite to that of one gate of the second selection gate pair, a first region of the semiconductor substrate between the opposite selection gates, side surfaces of the plurality of peripheral gates, and a second region of the semiconductor substrate disposed adjacent to the side surfaces of the peripheral gays;
removing the first insulation film on the first and the second region;
forming a second insulation film including nitrogen as the main component over a whole exposed surface;
forming an interlayer insulation film having a large etching selectivity to the second insulation film on the second insulation film;
etching the interlayer insulation film on the first region to form a contact hole;
and
filling a conductive material in the contact hole to connect the conductive material to one of the plurality of diffusion regions formed in the first region.

6 more elements

A semiconductor device comprising:

a semiconductor substrate;
a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate;
a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other;
a second diffusion region formed adjacent to and apart an end of the plurality of first diffusion regions formed in line on the semiconductor substrate;
a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions formed in line and the second diffusion region;
a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode;
a pair of third diffusion regions formed on the semiconductor substrate such that the peripheral gate electrode is formed between the third diffusion regions;
a first insulation film filled between adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes formed in line and the selection gate electrode, formed on a side surface of the peripheral gate electrode, including a main component other than nitrogen, and a thickness of the first insulating film between the memory cell gate electrodes being larger than thickness of the first insulation film formed on an upper half side surface of the peripheral gate electrode;
and
a second insulation film formed on at least the side surface of the peripheral electrode via the first insulation film and formed of a material different from that of the first insulation film.

7 more elements

A manufacturing method of a semiconductor device, comprising:

forming a first gate electrode layer, a first insulation film, and a second gate electrode layer on a semiconductor substrate in this order;
by processing the second gate electrode layer, the first insulation film, and the first gate electrode layer by lithography, forming a plurality of memory cell gate electrodes in a memory cell portion, while simultaneously forming a peripheral gate electrode in a peripheral circuit portion;
by using the plurality of memory cell gate electrodes as masks, forming a plurality of first diffusion regions on the semiconductor substrate;
forming a second insulation film so as to line the exposed surfaces of the plurality of memory cell gate electrodes of the memory cell portion, the semiconductor substrate exposed between the plurality of memory cell gate electrodes, the exposed surface of the peripheral gate electrode of the peripheral circuit portion, and the semiconductor substrate adjacent to an underpart of the peripheral gate electrode;
removing a portion of the second insulation film which covers the peripheral gate electrode;
forming a third insulation film so as to fill between the plurality of memory gate electrodes via the second insulation film and to simultaneously line the peripheral gate electrode;
and
by using the peripheral gate electrode as a mask, forming a pair of second diffusion regions on the semiconductor substrate.

5 more elements

Dependencies are inferred from the claim text.

Description12,856 words

Summary2,774 words

#This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-390993, filed Dec. 25, 2001; and No. 2002-072460, filed Mar. 15, 2002, the entire contents of both of which are incorporated herein by reference.

#1. Field of the Invention

#The present invention relates to a semiconductor device which includes a memory cell portion including a memory cell gate and selection gate and a peripheral circuit portion including a peripheral gate, and a manufacturing method of the semiconductor device.

Brief description of the drawings20 figures

#FIG. 1 is a plan view showing a layout of a memory cell portion of a conventional NAND type EEPROM;

#FIG. 2 is a sectional view of a prior-art NAND type EEPROM, corresponding to a section taken along line II-II of FIG. 1;

#FIG. 3 is a sectional view taken along line III-III of FIG. 1;

Detailed description9,687 words

#Prior to description of embodiments of the present invention, a configuration and problem of EEPROM will generally be described.

#For the EEPROM, a NAND type EEPROM shown in FIGS. 1 to 3 is known as a system suitable for a large-capacity memory. In a memory cell array of the EEPROM, a plurality of memory cell transistors are connected in series, one end is connected to a drain-side selection gate transistor 53, and the other end is connected to a source-side selection gate transistor 54. A well 51 is disposed on a portion of a semiconductor substrate 50, and a striped element region 55 is formed in the well. Each element region 55 is separated by an element isolation region 56. On the striped element region 55, a plurality of cell transistors including a stacked gate structure are arranged in columns, and cell transistors are arranged in a matrix form as the whole memory cell region. A peripheral circuit portion (not shown in FIG. 1) is disposed outside the memory cell region, and a peripheral gate 72 is disposed in the region (FIG. 2).

#Each memory cell includes a gate electrode portion 52 disposed on a gate insulation film 57 on the element region 55, and the gate electrode portion 52 is formed by stacking a floating gate electrode 58 as a charge accumulation layer, inter-gate insulation film 59, control gate electrode 60, and gate mask material 70. Furthermore, the control gate electrode 60 is connected to other gate electrodes in a row line direction, and forms a word line 61.

Facts

Application

10/326,179Filed 23 Dec 2002

Priority

JP 2001-39099325 Dec 2001

Published

14 Aug 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND

Timeline

25 Dec 2001Priority claimedJP 2001-390993
23 Dec 2002Application filedUS 10/326,179
14 Apr 2003Assigned to Kabushiki Kaisha Toshibaassignment of assignor's interest
14 Aug 2003Published
24 Aug 2017Assigned to Toshiba Memory Corporationassignment of assignor's interest
22 Jan 2021Assigned to K.K. Pangeamerger
22 Jan 2021Assigned to Toshiba Memory Corporationchange of name and address
22 Jan 2021Assigned to Kioxia Corporationchange of name and address

Semiconductor device and manufacturing method

Life of this patent

Semiconductor device and manufacturing method

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims29

Description12,856 words

Drawings

Classification6 codes

Life of this patent

Description12,856 words