Synchronization of data links in a multiple link receiver

A dual link receiver that terminates a primary link having a plurality of primary link channels and that terminates a secondary link having a plurality of secondary link channels, the receiver comprising:

• a primary link receiver comprising:
• a primary link front end that terminates a plurality of conductors carrying the plurality of primary link channels and that recovers the plurality of primary link channels;
• a primary link channel alignment block coupled to the primary link front end that receives the plurality of primary link channels and that channel aligns the plurality of primary link channels to produce a plurality of channel aligned primary link channels;
• a primary link alignment block coupled to receive the plurality of channel aligned primary link channels from the primary channel alignment block;
• a secondary link receiver comprising:
• a secondary link front end that terminates a plurality of conductors carrying the plurality of secondary link channels and that recovers the plurality of secondary link channels;
• a secondary link channel alignment block coupled to the secondary link front end that receives the plurality of secondary link channels and that channel aligns the plurality of secondary link channels to produce a plurality of channel aligned secondary link channels;
• and
• a secondary link alignment block coupled to receive the plurality of channel aligned secondary link channels from the secondary channel alignment block;
• and
• wherein the primary link alignment block and the secondary link alignment block interact to align the plurality of channel aligned secondary link channels with the plurality of channel aligned primary link channels.

An enabling circuit for indicating when a blanking period serviced by a three channel receiver has begun, the enabling circuit comprising:

• three AND logic gates, each of which receives as its input a pair of data enable signals produced by the three channel receiver;
• an OR logic gate coupled to receive as its input the outputs of each of the plurality of AND logic gates and produces a logic zero output that indicates when a blanking period has begun;
• and
• wherein at least one of the plurality of AND logic gates will produce a logic one unless at least two of the three data enable signals is logic zero such that the OR logic gate will not produce a logic zero output unless at least two of the three data enable signals is logic low.

A method for receiving and aligning dual high speed bit stream links comprising:

• recovering a plurality of primary link channels of a primary link;
• channel aligning the plurality of primary link channels to produce a plurality of channel aligned primary link channels;
• recovering a plurality of secondary link channels of a secondary link;
• channel aligning the plurality of secondary link channels to produce a plurality of channel aligned secondary link channels;
• and
• aligning the plurality of channel aligned secondary link channels with the plurality of channel aligned primary link channels.

A method for receiving and aligning dual high speed bit stream links comprising:

• bit recovering, synchronizing, and decoding the plurality of primary link channels of a primary link;
• channel aligning the plurality of primary link channels to produce a plurality of channel aligned primary link channels;
• bit recovering, synchronizing, and decoding the plurality of secondary link channels of a secondary link;
• channel aligning the plurality of secondary link channels to produce a plurality of channel aligned secondary link channels;
• determining a relative misalignment between the plurality of channel aligned primary link channels and the plurality of channel aligned secondary link channels;
• introducing a primary link delay into the plurality of channel aligned primary link channels;
• introducing a secondary link delay into the plurality of channel aligned secondary link channels;
• and
• wherein the difference between the primary link delay and the secondary link delay corresponds to the misalignment between the plurality of channel aligned primary link channels and the plurality of channel aligned secondary link channels.