System and method for simplifying clock construction and analysis

A system for simplifying clock construction and analysis of an integrated circuit, comprising:

• a memory;
• software stored within said memory defining functions to be performed by said system;
• and
• a processor, wherein said processor is configured by said software to perform the steps of:
• reading a defined location for a clock generator within said integrated circuit, wherein said clock generator generates a clock signal;
• reading a defined number of interconnect routes to be created within said integrated circuit, wherein a subset of said number of interconnect routes corresponds to a number of logical blocks that will later be provided within said integrated circuit, and wherein each of said interconnect routes within said subset comprises an open end for one of said logical blocks to be placed;
• testing electrical characteristics and functionality of said integrated circuit to ensure that a time for said clock signal to traverse each of said interconnect routes within said subset is equal, and changing properties within said integrated circuit if said clock signal traversal time is not equal;
• and
• adding one of said logical blocks to each one of said interconnect routes within said subset, wherein each said logical block is connected to said open end of one of said interconnect routes within said subset.

A system for simplifying clock construction and analysis of an integrated circuit, comprising:

• means for reading a defined location for a clock generator within said integrated circuit, wherein said clock generator generates a clock signal;
• means for reading a defined number of interconnect routes to be created within said integrated circuit, wherein a subset of said number of interconnect routes corresponds to a number of logical blocks that will later be provided within said integrated circuit, and wherein each of said interconnect routes within said subset comprises an open end for one of said logical blocks to be placed;
• means for testing electrical characteristics and functionality of said integrated circuit to ensure that a time for said clock signal to traverse each of said interconnect routes within said subset is equal, and changing properties within said integrated circuit if said clock signal traversal time is not equal;
• and
• means for adding one of said logical blocks to each one of said interconnect routes within said subset, wherein each said logical block is connected to said open end of one of said interconnect routes within said subset.