Verification of embedded test structures in circuit designs
AssigneeLogicVision, Inc.
InventorsPaul Price, Jean-Francois Cote, Ajit Kumar Verma
Life of this patent
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Abstract
A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
Claims58
A program product for use in generating test benches for verifying test structures embedded in a circuit, comprising:
- a verification specification processor for parsing a verification specification containing test specifications for selected test structures;
- a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
A method of generating test benches for a circuit having embedded test structures, comprising:
- generating a test connection specification identifying embedded test structures in said circuit;
- generating a verification specification having a specific verification section in which said test structures are grouped by test structure type and each test structure type group includes test structure type global parameters and parameters for each of predetermined test steps required to verify test structures in said group;
- and
- generating a test bench corresponding to each test structure type group.
A method for generating test benches for operationally verifying embedded test structures in a circuit, comprising:
- specifying embedded test structures to be verified;
- parsing a verification specification containing test specifications for test structures in said circuit, said test specifications being grouped by test structure type, each test structure type group containing test structure type global parameters, test step parameters for verifying test structures within said group and test structure specific parameters;
- and
- for each specified test structure type group, generating a test bench according to said global parameters, test parameters and test structure specific parameters.
Dependencies are inferred from the claim text.