US 2003/0149948 A1 · Circuit configuration of a chip with a graphic controller integrated and method for testing the same

Abstract

The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

Claims14

Dependent claims

A circuit configuration of a chip with a graphic controller integrated, comprising:

a main control module, including at least one front side bus (FSB) controller connected through a front side bus to a central process unit (CPU) and a memory controller connected through a memory bus to a memory;
a graphic controller, for processing the requests and operation for a graphic display, an accelerated graphic port and a graphic engine;
and
a test circuit, installed in said main control module so as to allow said graphic controller to be directly connected to said buses through said test circuit in a testing mode;
wherein, in said testing mode, said test circuit processes a plurality of testing data at a rate which is a plurality of times the data transmission rate of said graphic controller.

2 more elements

Dependencies are inferred from the claim text.

Circuit configuration of a chip with a graphic controller integrated and method for testing the same

Life of this patent

Circuit configuration of a chip with a graphic controller integrated and method for testing the same

Life of this patent

Abstract

Claims14