Method and system of data processor design
AssigneeMotorola, Inc.
InventorsMagdy S. Abadir, Andreas Veneris
Life of this patent
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Abstract
A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.
Claims35
A method comprising the steps of:
- modifying an element in a first design representation to create a second design representation, wherein the first design representation represents a first circuit having a first logic function and the second design representation represents a second circuit having a second logic function different than the first logic function;
- determining a first test vector to sensitize a logical difference between the first design representation and the second design representation;
- and
- determining a set of corrections based on the first test vector, wherein a correction within the set of corrections identifies a modified design representation logically the same as the first circuit for the first test vector.
A method comprising the steps of:
- determining a first test vector to sensitize a functionality difference between a first portion of a first design representation and a second portion of the first design representation;
- and
- determining a design representation modification based upon the first test vector, wherein the design representation modification is to be used in a device instead of the first portion and the second portion to provide a desired logical functionality.
A system comprising:
- a differential test vector generator having a first input to access a first design representation, a second input to access a second design representation, and an output to provide a test vector that sensitizes a logical difference between at least a portion of the first design representation and at least a portion of the second design representation;
- and
- a error correction module having a first input coupled to access the first design representation, a second input coupled to access the second design representation, a third input coupled to the output of the differential test vector generator, and an output to provide a third design representation that is logically equivalent to the first design representation based on the test vector.
A system comprising:
- a processing module;
- and
- memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:
- access a design representation having a first portion and a second portion;
- determine a test vector to sensitize a logical difference between the first portion and a second portion;
- and
- determine a design representation modification based upon the first test vector, wherein the design representation modification is to provide a desired functionality in place of the first portion and the second portion.
A computer readable medium for storing a data processing routine comprising the steps of:
- determining a test vector to sensitize a functionality difference between a first portion of a first design representation and a second portion of the first design representation;
- and
- determining a design representation modification based upon the test vector, wherein the design representation modification is to replace the first portion and the second portion to provide a desired logical functionality.
A method comprising the steps of:
- coupling a first node to a first data input of a first multiplexing circuit, wherein the functionality of the first node is based upon a first circuit;
- coupling a second node to a second data input of the first multiplexing circuit, wherein the functionality of the second node is based upon a second circuit;
- and
- performing a stuck-at analysis at the select input of the first multiplexing circuit to determine logical equivalency of the first circuit and the second circuit.
A method comprising the steps of:
- coupling a first node to a first data input of a first multiplexing circuit, wherein the functionality of the first node is based upon a first circuit;
- coupling a second node to a second data input of the first multiplexing circuit, wherein the functionality of the second node is based upon a second circuit;
- and
- performing a stuck-at analysis at the select input of the first multiplexing circuit to determine a set of test vectors to sensitize logical differences between the first circuit and the second circuit.
Dependencies are inferred from the claim text.