Semiconductor integrated circuit device having pipeline stage and designing method therefor

A semiconductor integrated circuit device comprising:

• a first flip-flop circuit for transferring a received signal synchronously with a clock signal;
• a first latch circuit operating complementarily to said first flip-flop circuit and synchronously with said clock signal, for transferring and latching a signal applied thereto;
• a first logic circuit arranged between said first flip-flop circuit and said first latch circuit, performing a logic processing on a signal applied from at least said first flip-flop circuit, and transferring a resultant signal to said first latch circuit;
• a second latch circuit operating complementarily to said first latch circuit and synchronously with said clock signal, and transferring and latching a signal applied thereto;
• a second logic circuit arranged between said first latch circuit and said second latch circuit, performing a logic processing on a signal from said first latch circuit, and transferring a resultant signal to said second latch circuit;
• a second flip-flop circuit operating complementarily to said second latch circuit and synchronously with said clock signal, for transferring a signal applied thereto;
• and
• a third logic circuit arranged between said second latch circuit and said second flip-flop circuit, performing a logic processing on a signal received from said second latch circuit, and transferring a resultant signal to said second flip-flop circuit,
• said first and second latch circuits and said first and second flip-flop circuits being arranged so as to satisfy the following conditions:
• L1≦TK−TPDF1−SUPL1+SKW1−SKET−JTR (1);L2≦TK−TPDL1−SUPL2+SKW2−SKET−JTR (2);L3≦TK−TPDL2−SUPF2+SKW3−SKET−JTR (3);L1+L2≦(1+HDY)•TK−TPDF1−SUPL2 +SKW4−SKET−JTR•K1−THR1 (4);L2+L3≦(1+LDY)•TK−TPDL1−SUPF2+SKW5 −SKET−JTR•K2−THR2 (5);L1+L2+L3≦2•TK−TPDF1−SUPF2+SKWA −SKET−JTR•K3−THR1−THR2 (6);L1≧HLDL1−TPDFH1+SKWH1+SKETH (7);L2≧HLDL2−TPDLH1+SKWH2+SKETH (8);
• andL3≧HLDF2−TPDLH2+SKWH3+SKETH (9),
• in which, L1, L2 and L3 indicate logic delay time of the first, second and third logic circuits, respectively;
• TK indicates the cycle period of said clock signal;
• TPDF1 indicates a delay of a signal output of said first flip-flop circuit from said clock signal;
• TPDL1 and TPDL2 indicate delays of output signals of the first and second latch circuits relative to said clock signal, respectively;
• SKW1, SKW2 and SKW3 indicate skews of said clock signal for a clock signal applied to the circuit at a preceding stage;
• SKW4 indicates a skew of the clock signal applied to said second latch circuit for the clock signal applied to said first flip-flop circuit;
• SKW5 indicates the skew of the clock signal applied to said first latch circuit for the clock signal applied to said second flip-flop circuit;
• SKWA indicates the skew of the clock signal applied to said second flip-flop circuit for the clock signal applied to said first flip-flop circuit;
• SUPL1, SUPL2 and SUPF2 indicate setup time of said first latch circuit, setup time of said second latch circuit, and setup time of said second flip-flop circuit, respectively;
• SKET indicates a fixed skew due to an uncertain factor of said clock signal;
• JTR indicates a jitter of said clock signal for the clock signal of a circuit at a preceding stage;
• THR1 and THR2 indicate signal propagation delay time of said first latch circuit and signal propagation delay time of said second latch circuit, respectively;
• HDY and LDY indicate duties of the clock signal for the first and second latch circuits in a latching period, respectively;
• K1, K2 and K3 indicate coefficients indicating a cycle period dependency of said jitter;
• HLDL1 and HLDL2 and HLDF2 indicate hold time of said first latch circuit, said second latch circuit and said second flip-flop circuit for said clock signal, respectively;
• TPDFH1, TPDLH1 and TPDLH2 indicate delays of output signals of said first flip-flop circuit, said first latch circuit and said second latch circuit relative to input of said clock signal with respect to hold conditions, respectively;
• SKWH1, SKWH2 and SKWH3 indicate skews of said clock signal for a clock signal applied to the circuit at the preceding stage with respect to the hold conditions;
• and SKETH indicates a fixed skew caused by the uncertain factor of said clock signal.

A semiconductor integrated circuit device comprising:

• a first flip-flop circuit for transferring an applied signal synchronously with a clock signal;
• a first logic circuit performing a logic processing on the signal received from said first flip-flop circuit;
• a first latch circuit operating complementarily to said first flip-flop circuit and synchronously with said clock signal, and transferring and latching an output signal of said first logic circuit;
• a second logic circuit performing a logic processing on the signal received from said first latch circuit;
• a second latch circuit operating complementarily to said first latch circuit and synchronously with said clock signal, and transferring and latching an output signal of said second logic circuit;
• a third logic circuit performing a logic processing on an output signal of said second latch circuit, and outputting a resultant signal;
• a third latch circuit operating complementarily to said second latch circuit and synchronously with said clock signal, and transferring and latching the output signal of said third logic circuit;
• a fourth logic circuit performing a logic processing on the signal received from said third latch circuit, and outputting a resultant signal;
• a fourth latch circuit operating complementarily to said third latch circuit and synchronously with said clock signal, and transferring and latching the resultant signal of said fourth logic circuit;
• a fifth logic circuit performing a logic processing on an output signal of said fourth latch circuit, and outputting a resultant signal;
• and
• a second flip-flop circuit operating, in a common phase with said fourth latch circuit, synchronously with said clock signal, and transferring the output resultant signal of said fifth logic circuit,
• logic delay time L1 to L5 of the first to fifth logic circuits satisfying following conditions:
• L1≦TK−TPDF1−SUPL1+SKW1−MRG (1);L2≦TK−TPDL1−SUPL2+SKW2−MRG (2);L3≦TK−TPDL2−SUPL3+SKW3−MRG (3);L4≦TK−TPDL3−SUPL4+SKW4−MRG (4);L5≦TK−TPDL4−SUPF2+SKW5−MRG (5);L1+L2≦(1+HDY)•TK−TPDF1−SUPL2−SKW21−MRGJ1−THR1 (6);L2+L3≦(1+LDY)•TK−TPDL1−SUPL3−SKW22−MRGJ2−THR2 (7);L3+L4≦(1+HDY)•TK−TPDL2−SUPL4−SKW23−MRGJ1−THR3 (8);L4+L5≦(1+LDY)•TK−TPDL3−SUPF2−SKW24−MRGJ2−THR4 (9);L1+L2+L3≦2•TK−TPDF1−SUPL3−SKW31−MRGJ3 −THR1−THR2 (10);L2+L3+L4≦2•TK−TPDL1−SUPL4−SKW32−MRGJ3 −THR2−THR3 (11);L3+L4+L5≦2•TK−TPDL2−SUPF2−SKW33−MRGJ3 −THR3−THR4 (12);L1+L2+L3+L4≦(2+HDY)•TK−TPDF1−SUPL4−SKW41 −MRGJ4−THR1−THR2−THR3 (13);L2+L3+L4+L5≦(2+LDY)•TK−TPDL1−SUPF2−SKW42 −MRGJ5−THR2−THR3−THR4 (14);L1+L2+L3+L4+L5≦3•TK−TPDF1−SUPF2−SKW51−MRGJ −THR1−THR2−THR3−THR4 (15);L1≧HLDL1−TPDFH1+SKWH1+MRGH (16);L2≧HLDL2−TPDLH1+SKWH2+MRGH (17);L3≧HLDL3−TPDLH2+SKWH3+MRGH (18);L4≧HLDL4−TPDLH3+SKWH4+MRGH (19);
• andL5≧HLDF2−TPDLH4+SKWH5+MRGH (20),
• in which, TK indicates a cycle period of said basic clock signal;
• TPDF1 indicates delay time of the output signal of said first flip-flop circuit relative to input of said clock signal;
• TPDL1 to TPDL4 each indicate delays of output signals of the first to fourth latch circuits relative to a corresponding trigger edge of said clock signal;
• SUPL1 to SUPL4 indicate setup time of the first to fourth latch circuits with respect to said clock signal;
• SUPF2 indicates a setup time of said second flip-flop circuit with respect to said clock signal;
• SKW1 to SKW5 indicate skews of said clock signal for a clock signal applied to a circuit at a preceding stage;
• SKW21 to SKW24 indicate skews of clock signals for consecutive two stages of logic circuits of the first to fifth logic circuits;
• SKW31 to SKW33 indicate skews of clock signals for consecutive three stages of logic circuits of the first to fifth logic circuits;
• SKW41 and SKW42 indicate skews of clock signals for consecutive four stages of logic circuits of the first to fifth logic circuits;
• SKW51 indicates a skew of a clock signal applied to said second flip-flop circuit with respect to a clock signal applied to said first flip-flop circuit;
• THR1 to THR4 indicate signal propagation delay time of the first to fourth latch circuits;
• HDY indicates a duty of said clock signal for a latching state of each of the first and third latch circuits;
• LDY indicates a duty of said clock signal for a latching state of each of the second and fourth latch circuits;
• MRG indicates a margin for a component including jitter of said clock signal;
• MRGJ1 to MRGJ5 indicate margins for said clock signal with cycle period dependency of said jitter taken into account;
• HLDL1 to HLDL4 indicate hold time of the first to fourth latch circuits for said clock signal;
• HLDF2 indicates a hold time of said second flip-flop circuit for said clock signal;
• TPDF1 indicates a delay of the output signal of said first flip-flop circuit relative to a trigger edge of said clock signal with respect to hold conditions;
• TPDLH1 to TPDLH4 indicate delays of output signals of the first to fourth latch circuits relative to a corresponding trigger edge of said clock signal;
• SKWH1 to SKWH5 indicate skews of said clock signal for a clock signal applied to the circuit at the preceding stage with respect to the hold conditions;
• and MRGH indicates the margin for said clock signal with respect to the hold conditions.