Check bit free error correction for sleep mode data retention
AssigneeInternational Business Machines Corporation
InventorKraig R. White
Life of this patent
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Abstract
A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding occurs at the time of entering the sleep mode and ECC decoding for error detection and correction need only take place upon wake up when resuming active mode. In addition, the memory system reassigns a portion of the memory for storing the additional parity bits required for the error correcting code (ECC).
Claims20
A memory system having a reduced refresh rate in a sleep mode, comprising:
- a dynamic memory;
- an error correction code (ECC) memory allocation circuit for identifying non-critical bit addresses in said dynamic memory and allocating said addresses as ECC addresses when entering from an active mode to sleep mode;
- an ECC encoder for encoding critical bits with error correction codes, said error correction codes being stored in said ECC addresses;
- a refresh execution circuit for reducing said refresh rate in said sleep mode and increasing said refresh rate in said active mode;
- and
- a ECC decoder for decoding said critical bits encoded with said error correction codes when reentering said active mode.
A method for reducing the refresh rate of a memory in sleep mode, comprising the steps of:
- switching from an active mode to a sleep mode;
- identifying non-critical bit addresses;
- encoding critical bits with an error correction code (ECC);
- storing ECC codes at said non-critical bit addresses;
- reducing a refresh rate for said memory;
- performing error correction on said critical bits using said ECC codes when reentering active mode;
- and
- discarding said ECC bits.
A computer readable medium embodying instructions for causing a computer to take steps to reduce the refresh rate of a memory in sleep mode, the steps comprising:
- switching from an active mode to a sleep mode;
- identifying non-critical bit addresses;
- encoding critical bits with an error correction code (ECC);
- storing ECC codes in said non-critical bit addresses;
- reducing a refresh rate for said memory;
- performing error correction on said critical bits using said ECC codes when reentering active mode;
- and
- discarding said ECC bits.
Dependencies are inferred from the claim text.