Low hardware overhead scan based 3-weight weighted random BIST architectures
AssigneeNEC Corporation
InventorSeongmoon Wang
Life of this patent
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Abstract
Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved automatic test pattern generator. The improved automatic test pattern generator is adapted to consider hardware overhead and test sequence lengths, the hardware overheads being incurred when each new testcube is added to the test set. Parallel and serial type test per scan built-in self test circuits designed and adapted to use the disclosed improved automatic test pattern generator are also disclosed.
Claims35
A method for generating a test set for hard to detect faults, said method comprising:
- a) identifying a set of hard to detect faults;
- and
- b) generating the test set for the hard to detect faults by using an automatic test pattern generator;
- wherein, the automatic test pattern generator comprises functionality for a global generator and is adapted to consider hardware overhead and test sequence lengths, said hardware overheads being incurred when each new testcube is added to the test set.
A method of generating test sets for a fault list comprising hard to detect faults, the method comprising:
- (a) initializing i←0 and glob_gen←{N,N, . . . ,N);.
- (b) initializing a current testcube set, Ci←φ;
- (c) unmarking all faults in the fault list;
- (d) initializing a current generator, gen(Ci)={X,X, . . . ,X} and j←0;
- (e) if there are no more faults in the fault list, then proceeding to step (m);
- (f) generating a testcube cj using an ATPG;
- (g) adding the testcube cj to a current testcube set, Ci<-Ci U cj;
- (h) mark faults detected by the testcube cj;
- (i) setting j<-j+1;
- (k) if the number of conflicting inputs of any testcube in Ci is greater than a positive integer M then Ci←CI−cj, i←i+1, updating the global generator, and proceeding to step (b);
- (l) if the number of conflicting inputs of any testcube in Ci is not greater than M, updating gen(Ci) and proceeding to step (e);
- (m) generating 3-weight weighted random pattern testing (WRPT) patterns by fixing inputs or applying pure random patterns to inputs according to gen(Ci);
- and
- (n) running fault simulation to drop the faults that are detected by the generated 3-weight WRPT patterns.
A parallel type test per scan built-in self test circuit comprising:
- a circuit under test comprising inputs;
- a set of scan flip flops that are connected to the inputs, each of said scan flip flops having at least a synchronous reset (R) or a synchronous preset (S) pin;
- a LFSR for loading random vectors that provide input to the set of scan flip-flops;
- a decoder providing decoder outputs, wherein said decoder outputs control the R and S pins in the scan flip-flops, said decoder comprising a functionality of a global generator;
- a counter providing inputs to the decoder that determine a state of the decoder outputs;
- and
- an enable input for the decoder,
- wherein the decoder provides overriding signals to by controlling the input to the R and S pins, said overriding signals overriding the random vectors based on tests in a generator for test patterns for hard faults, said tests being generated by an automatic test pattern generator.
A serial type test per scan built-in self-test circuit comprising:
- a circuit under test comprising inputs;
- a set of scan flip flops that are connected to the inputs;
- a LFSR for loading random vectors that provide input to the set of scan flip-flops;
- an AND gate and an OR gate inserted between said LFSR and the set of scan flip flops;
- a decoder providing two decoder output signals D0 and D1, said decoder output signals being input to the AND and OR gates;
- a generator counter that selects a generator providing inputs to the decoder;
- a scan counter that provides input to the decoder, wherein a state of the decoder outputs are together determined by the counter input and the scan counter input;
- and
- an enable input for the decoder,
- wherein the decoder provides overriding signals, said overriding signals overriding the random vectors based on tests in a generator for test patterns for hard faults, said tests being generated by an automatic test pattern generator.
The circuit of cliam 33 wherein compatible overriding signals are merged prior to applying genetic algorithms.
Dependencies are inferred from the claim text.