Single scan chain in hierarchiacally bisted designs
OwnerKrishna B. Rajaninventor
Life of this patent
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Abstract
Disclosed are novel methods and apparatus for efficiently providing a single scan chain design for hierarchically BISTed designs. In an embodiment, a method of providing a single scan chain of a chip is disclosed. The method includes: selecting a TOP chain of the chip, the chip being divided into a plurality of embedded logic test (ELT) blocks; bypassing periphery flops of the plurality of ELT blocks; selecting a single scan chain of all ELT blocks of the chip; and inserting the single scan chain of all ELT blocks of the chip into the TOP chain of the chip.
Claims33
A method of providing a single scan chain of a chip, the method comprising:
- selecting a TOP chain of the chip, the chip being divided into a plurality of embedded logic test (ELT) blocks;
- bypassing periphery flops of the plurality of ELT blocks;
- selecting a single scan chain of all ELT blocks of the chip;
- and
- inserting the single scan chain of all ELT blocks of the chip into the TOP chain of the chip.
An apparatus comprising:
- a first selector to select a TOP chain of a chip, the chip being divided into a plurality of embedded logic test (ELT) blocks;
- a bypassing mechanism to bypass periphery flops of the plurality of ELT blocks;
- a second selector to select a single scan chain of all ELT blocks of the chip;
- and
- a combiner to combine the single scan chain of all ELT blocks of the chip with the TOP chain of the chip,
- wherein the apparatus provides a single scan chain of the chip.
An apparatus for providing a single scan chain of a chip, the apparatus comprising:
- first selection means to select a TOP chain of the chip, the chip being divided into a plurality of embedded logic test (ELT) blocks;
- bypassing means for bypassing periphery flops of the plurality of ELT blocks;
- second selection means to select a single scan chain of all ELT blocks of the chip;
- and
- inserting means to insert the single scan chain of all ELT blocks of the chip into the TOP chain of the chip.
An article of manufacture comprising:
- a machine readable medium that provides instructions that, if executed by a machine, will cause the machine to perform operations including:
- selecting a TOP chain of a chip, the chip being divided into a plurality of embedded logic test (ELT) blocks;
- bypassing periphery flops of the plurality of ELT blocks;
- selecting a single scan chain of all ELT blocks of the chip;
- and
- inserting the single scan chain of all ELT blocks of the chip into the TOP chain of the chip,
- wherein the operations provide a single scan chain of the chip.
Dependencies are inferred from the claim text.