Method and apparatus for detecting faults on integrated circuits

A scan device for detecting faults in a logic circuit, comprising:

• a first plurality of input scan-cells for receiving a scan pattern and presenting said scan pattern to said logic circuit when a control signal is in a first state, each input scan-cell comprising:
• a first multiplexer for providing a first signal at a first output thereof, said first signal corresponding to a first data signal when a control signal is in a first state and said first signal corresponding to a scan pattern signal when said control signal is in a second state;
• a switching device having an input coupled to said first output for capturing said first signal and having a second output for providing a second signal;
• and
• a second multiplexer having an input coupled to said second output for transmitting said second signal when said control signal is in said first state and for transmitting an inverted form of said second signal when said control signal is in said second state;
• and
• a plurality of output scan-cells coupled to said logic circuit for capturing the results of said logic circuit operating on said scan pattern.

A method for detecting faults in a logic circuit comprising:

• presenting a test signal to said logic circuit when a control signal is in the first state;
• inverting said test signal when the control signal transitions from the first state to a second state to create a measuring edge;
• capturing an output of said logic circuit in a second storage device, said output being responsive to the inverted test signal;
• and
• measuring the time between said measuring edge and the capture of said output.

A method for detecting faults in a logic circuit, comprising:

• storing a scan pattern in a first plurality of input scan-cells;
• presenting said scan pattern stored in said plurality of input scan-cells to said logic circuit when a control circuit is in a first state;
• inverting said scan pattern presented to said logic circuit when said control circuit transitions from the first state to a second state to create a measuring edge;
• capturing an output of said logic circuit in a second plurality of output scan-cells;
• and
• measuring the delay between said measuring edge and the capture of the output of said logic circuit.