Embedded testing capability for integrated serializer/deserializers

An integrated circuit comprising:

• a substrate;
• core circuitry integrated onto said substrate;
• a plurality of SERDESs integrated onto said substrate, each said SERDES having parallel data inputs and parallel data outputs and having serial data inputs and outputs;
• a plurality of functional test interfaces (FTIs) integrally formed with said substrate, each said FTI being uniquely associated with one of said SERDESs and being connected to said parallel data inputs and outputs of said associated SERDES, said FTIs being enabled to individually and concurrently test performances of said SERDESs;
• a plurality of functional test controllers (FTCS) integrally formed with said substrate, each said FTC being uniquely associated with one of said FTIs and being configured to select among operational modes of said associated FTI;
• and
• an input/output controller (IOC) integrally formed with said substrate, said IOC being connected to each said FTC to transmit individually addressed commands to each said FTC, said IOC further being connected to exchange signals with an external device.

A method of testing operations of serializer/deserializers (SERDESs) of an integrated circuit comprising the steps of:

• embedding a plurality of test interfaces within said integrated circuit such that each test interface is specific to one said SERDES with respect to exchanging parallel data;
• embedding test controllers within said integrated circuit such that each said test controller is specific to one said test interface with respect to triggering test operations by said test interface;
• and
• providing an integrated circuit output that enables said test controllers to be individually addressed.