Fault verification apparatus
OwnerHideyuki Ohtake, Yoshikazu Akamatsuinventors
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Abstract
A fault verification apparatus performs a logic simulation of a circuit having a normal delay and a logic simulation of a circuit in which delay is intentionally changed for a node and compares the simulation results at a specific time and checks whether or not a test pattern can detect a fault due to a delay abnormality. The apparatus performs the logic simulation by applying the test pattern to the normal circuit and a variety of fault types and compares the expected values obtained from the results of the respective logic simulations and verifies whether or not the test pattern can detect the delay fault by whether or not the expected values are different from each other at a specific comparison point.
Claims6
A fault verification apparatus:
- means for inputting circuit information of a semiconductor circuit and for drawing a fault point;
- means for performing a logic simulation through a normal circuit by use of a test pattern and for defining the simulation results as a first expected value;
- means for specifying a fault-generated point from said fault point and for generating a predetermined delay fault and for inserting the delay fault at said fault-generated point to produce a fault circuit;
- means for performing a logic simulation through said fault circuit by use of said test pattern and for defining the simulation results as a second expected value;
- and
- means for comparing the first expected value through the normal circuit with the second expected value through the fault circuit at a specific time.
Dependencies are inferred from the claim text.