Testability analysis system and method, and design for testability system and method

A testability analysis method, comprising the steps of:

• inputting functional description data to define a hardware function;
• identifying register variables whereby memory elements in said functional description data are inferred;
• conducting a simulation by applying random patterns to said register variables identified;
• and
• analyzing a cause of decrease of a fault coverage by Scan-Based Logic BIST based upon toggle rates and simulation events of variables such as net and bus in said functional description data in accordance with a result of said simulation.

A design for testability system, comprising:

• an input part inputting functional description data to define a hardware function;
• a register variable identifying part identifying register variables whereby memory elements in said functional description data are inferred;
• a constraint setting part setting constraints for Scan-Based Logic BIST;
• a random pattern generator applying random patterns to the register variables identified by said register variable identifying part based upon said constraints;
• a simulator conducting a simulation of events caused by applying the random patterns;
• and
• an evaluation part evaluating whether or not an X is propagated in said functional description data and captured into the register variables identified by said register variable identifying part from a result of said simulation.

A design for testability method, comprising the steps of:

• inputting functional description data to define a hardware function;
• identifying register variables whereby memory elements in said functional description data are inferred;
• conducting a simulation by applying random patterns to said register variables identified under constraints for Scan-Based Logic BIST;
• and
• evaluating whether or not an X is propagated in said functional description data and captured into the register variables from a result of said simulation.

A design for testability method, comprising the steps of:

• inputting functional description data to define a hardware function;
• identifying register variables whereby memory elements in said functional description data are inferred;
• conducting a simulation by applying random patterns to said register variables identified;
• analyzing a cause of decrease of a fault coverage by Scan-Based Logic BIST based upon toggle rates and simulation events such as net and bus in said functional description data in accordance with a result of said simulation;
• and
• setting an alternate path of data for any signal in said functional description data by using a test mode signal as a selector for a net whose fault coverage is not sufficient based upon the analysis result.