Semiconductor integrated circuit with security function
AssigneeSamsung Electronics Co., Ltd.
InventorJong-Cheol Kim
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Abstract
An IC (integrated circuit) card (or smart card) comprising a plurality of detectors for detecting abnormal operating conditions of the IC card. If an abnormal condition is detected by one of the detectors, the detector will generate a detection signal, which is then stored in a nonvolatile memory. A reset signal is then generated in response to the detection signal to reset a central processor unit. The central processor unit informs a user of a reset status and a cause thereof.
Claims25
A semiconductor integrated circuit having a central processor unit, comprising:
- a plurality of detectors, wherein each detector detects a corresponding operating condition of the integrated circuit and generates a detection signal that indicates an abnormal condition;
- a reset signal generator for generating a reset signal in response to a detection signal output from one of the detectors;
- and
- a nonvolatile memory for storing detection signals output from the detectors;
- wherein the central processor unit is reset in response to the reset signal after the detection signals have been stored in the nonvolatile memory.
An IC (integrated circuit) card, comprising:
- an embedded CPU (central processing unit);
- a plurality of detectors, wherein each detector detects a corresponding operating condition of the IC card and generates a detection signal that indicates an abnormal condition;
- a reset signal generator for generating a reset signal in response to a detection signal output from one of the detectors;
- and
- a nonvolatile memory for storing detection signals output from the detectors;
- wherein the CPU is reset in response to the reset signal after the detection signals have been stored in the nonvolatile memory.
A method for monitoring operation of an integrated circuit, comprising the steps of:
- detecting a plurality of operating conditions of an integrated circuit;
- generating and storing a detection signal if an abnormal operating condition is detected;
- generating a reset signal in response to the detection signal;
- resetting a CPU (central processing unit) in response to the reset signal after the detection signal has been stored;
- and
- outputting the stored detection signal after resetting the CPU.
Dependencies are inferred from the claim text.