Automatic reset signal generator integrated into chipset and chipset with reset completion indication function
AssigneeVIA Technologies, Inc.
InventorScott Lin
Life of this patent
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Abstract
A circuit for automatically resetting a central processing unit (CPU) is provided. The circuit includes a detector and a reset signal generator. The detector is electrically connected to the CPU for receiving a specified signal from the CPU, and the detector sends out a triggering signal when the specified signal is not received for a predetermined period of time. The reset signal generator is electrically connected to the detector for generating a reset signal in response to the triggering signal. A chipset with a reset completion indication function is also provided. The chipset includes a plurality of functional circuits and a calculating and recording device.
Claims24
A circuit for automatically resetting a central processing unit (CPU), said circuit comprising:
- a detector electrically connected to said CPU for receiving a specified signal from said CPU, said detector sending out a triggering signal when said specified signal is not received for a predetermined period of time;
- and
- a reset signal generator electrically connected to said detector for generating a reset signal to reset said CPU in response to said triggering signal.
A circuit for automatically resetting a central processing unit (CPU), said circuit, comprising:
- a detector electrically connected to said CPU, sending out a triggering signal when detecting a specified operation of said CPU has suspended for a predetermined period of time;
- and
- a reset signal generator electrically connected to said detector, and generating a reset signal in response to said triggering signal to reset said CPU.
A chipset with a reset completion indication function, comprising:
- a plurality of functional circuits, respectively performing reset operations in response to reset signals, and outputting reset completion signals after completing said reset operations;
- and
- a calculating and recording device, calculating and recording said reset completion signals to indicate reset completion of said chipset.
Dependencies are inferred from the claim text.