Method and circuit arrangement for monitoring the operation of a processor

A method for monitoring the operation of a processor comprising the following method steps:

• altering a count variable of a counter by a predetermined value by a clock signal which is generated by a clock generator,
• if program execution in the processor is correct, then resetting the count variable to a predetermined start value at intermittent intervals of time by a reset signal from the processor,
• if the count variable reaches a first limit value, then using a first output of the counter to transmit an interrupt signal to an interrupt input of the processor,
• if the count variable reaches a second limit value, then using a second output of the counter to transmit a hardware reset signal to the hardware reset input of the processor, and
• after transmission of the hardware reset signal, resetting the counter whereby the count variable is assigned a predetermined start value.

A circuit arrangement for carrying out a method for monitoring the operation of a processor, comprising:

• a processor having at least two inputs, an interrupt input and a hardware reset input, and at least one output,
• a counter having at least two outputs and a reset input, with the counter being clocked by the clock signal from a clock generator,
• wherein a first output of the counter is electrically connected to the interrupt input of the processor, a second output of the counter is electrically connected to the hardware reset input of the processor, and the reset input is electrically connected to the output of the processor, as a result of which, if program execution is correct, the counter is reset to a predetermined start value at intermittent intervals of time by a reset signal from the processor,
• wherein, upon reaching a first limit value, the counter alters the potential at the first output and thus sends an interrupt signal to the processor, which, after the arrival of the interrupt signal, restarts the program or jumps to a prescribed location in the program,
• wherein, upon reaching a second limit value, the counter alters the potential at the second output and thus sends a hardware reset signal to the processor, which then performs a hardware reset,
• wherein the circuit arrangement comprises a switching unit which uses a change of potential at the reset input to reset the counter to a predetermined start value, and, while there is no reset signal from the processor, the circuit arrangement thus cyclically sends the interrupt signal and the hardware reset signal to the processor, and
• wherein the second output of the counter is electrically connected to the reset input of the counter.