Unbuffered memory system

A memory controller for use a memory system, wherein:

• said memory controller comprises an unbuffered memory module mounted thereon with a plurality of memory devices, a signal bus connected to said unbuffered memory module, and an external resistance element connected in series to said signal bus, and sends the same command/address signal to all of said memory devices mounted on said unbuffered memory module via said signal bus;
• and
• said memory controller further comprises an output terminal for outputting said command/address signal, an output transistor, and an internal resistance element inserted in series between an output end of said output transistor and said output terminal of said memory controller;
• wherein a resistance value of said internal resistance element is selected taking into account an on-resistance value of said output transistor and a resistance value of said external resistance element such that when seeing the side of said memory controller from a connection point between said external resistance element and said signal bus, an output impedance with respect to said command/address signal is maintained substantially constant in an operating voltage range of said command/address signal.

A method of designing an unbuffered memory module for use in an unbuffered memory system comprising the unbuffered memory module mounted thereon with a plurality of memory devices, a memory controller for sending the same command/address signal to all of said memory devices mounted on said memory module, and a signal bus connecting between said memory module and said memory controller to propagate said command/address signal from said memory controller to said memory module, wherein when there are a plurality of cases with respect to the expected numbers of said memory devices mounted on said memory module in said unbuffered memory system, even if a memory module with any number, in said expected numbers, of the mounted memory devices is incorporated into said unbuffered memory system, the take-in margin of said command/address signal in said memory devices can be secured, said method comprising:

• a first step of determining an initial layout including a wiring layout with respect to each of unbuffered memory modules corresponding to said plurality of cases;
• a second step of measuring a transfer delay time of a command/address signal according to each initial layout determined at the first step;
• a third step of setting one of the unbuffered memory modules of the plurality of cases for which the initial layouts are determined at the first step, as a specific unbuffered memory module;
• a fourth step of, based on the transfer delay times measured at the second step, deriving differences between the transfer delay time corresponding to said specific unbuffered memory module and the transfer delay times corresponding to the other unbuffered memory modules;
• and
• a fifth step of, based on the differences in transfer delay time derived at the fourth step, changing said initial layout of the corresponding unbuffered memory module in said unbuffered memory modules other than said specific unbuffered memory module, such that the corresponding difference is reduced to substantially zero.