Interleaving apparatus and method for a communication system

A method for interleaving input data with N=2m×j+a (where 0<a<2m) in a communication system, the method comprising the steps of:

• determining addresses in a sequential direction of a memory with an R×C matrix structure of N′=2m×(j+1);
• storing the input data in a sequential direction in the memory from an address 0 to an address N−1, and wherein no input data is stored in (2m−a) areas corresponding to addresses of N to N′−1 in a last column of the memory;
• generating output addresses with the R×C matrix structure by Partial Bit Reversal Order (PBRO)-interleaving the determined addresses;
• and
• generating a read address for reading data stored in the memory by determining the output addresses in the sequential direction, wherein the generated read address excludes output addresses corresponding to the addresses of N to N′−1.

An interleaving apparatus comprising:

• a counter, adapted to count addresses of 0 to N′−1 according to a new interleaver size N′=2m×(j+1), if a given interleaver size N is larger than 2m×j and smaller than 2m×(j+1);
• a memory, adapted to sequentially store N input data bits from an address 0 to an address N−1, based on the counting result by the counter;
• and
• an address generator, adapted to generate a read address for reading data stored in the memory by Partial Bit Reversal Order (PBRO) interleaving, wherein the generated read readdress excludes addresses corresponding to addresses of N to N′−1.

An interleaving apparatus in a communication system, the apparatus comprising:

• a memory with an R×C matrix structure of N′=2m×(j+1);
• a write address generator;
• and
• a read address generator;
• wherein the write address generator is adapted to generate a read address for reading input data with N=2mxj+a (where 0<a<2m) in a sequential direction in the memory from an address 0 to an address N−1;
• wherein no input data is stored in (2m−a) areas corresponding to addresses of N to N′−1 of the memory;
• wherein the read address generator is adapted to generate a read address for reading data stored in the memory by determining in the sequential direction output addresses with an R×C matrix structure generated by PBRO interleaving the addresse 0 to N−1, wherein the generated read address excludes output addresses corresponding to the addresses of N to N′−1.

A computer-readable medium of instructions, adapted to control an interleaver, the instructions comprising:

• a first set of instructions, adapted to control an interleaver to determine a new interleaver size N′=2m×(j+1) and addresses of 0 to N′−1, if a given interleaver size N is larger than 2m×j and smaller than 2m×(j+1),;
• a second set of instructions, adapted to control said interleaver to sequentially store N input data bits in a memory with the size N′ from an address 0 to an address N−1;
• a third set of instructions, adapted to control said interleaver to perform a Partial Bit Reversal (PBRO)-interleaving the memory with the size N′;
• and
• a fourth set of instructions, adapted to control said interleaver to read data from said memory by discarding addresses corresponding to addresses of N to N′−1.