Access control device for bus bridge circuit and method for controlling the same

An access control device for a bus bridge circuit connected between a first bus and a second bus and provided with a status controller for determining a state of access to both buses, comprising:

• a number-of-waits setting circuit for determining a wait periodicity corresponding to an operating speed of each of peripheral devices connected to the second bus according to an address corresponding to an access request to the second bus sent from the first bus, in response to the access request;
• a count value generator for generating a count value up to the wait periodicity set to the number-of-waits setting circuit;
• a control signal holding circuit for holding a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintaining the access state of the status controller;
• and
• a clock control circuit for dividing a clock for the first bus according to the wait periodicity set to the number-of-waits setting circuit and outputting the result of division to the second bus.

Abus bridge circuit connected between a first bus and a second bus, the bus bridge circuit comprising:

• a number-of-waits setting circuit which determines a wait periodicity corresponding to an operating speed of each of peripheral devices connected to the second bus in response to an address signal, the address signal being sent from the first bus and specifying corresponding peripheral devices;
• a count value generator which generates a count value up to the wait periodicity set to the number-of-waits setting circuit;
• and
• a clock control circuit which divides a clock for the first bus according to the wait periodicity set to the number-of-waits setting circuit and outputs the result of division to the second bus.

A method for controlling a bus bridge circuit for controlling a transfer of a signal between a first bus and a second bus, the method comprising;

• determining a dividing ratio corresponding to an operating speed of each of peripheral devices connected to the second bus in response to an address signal, the peripheral device being specified by an address signal;
• dividing a clock for the first bus by the dividing ratio and outputting the divided clock to the second bus;
• and
• allowing the first bus to stand by over a clock cycle determined according to the operating speed of the peripheral device.