Clock generation for multiple secondary buses of a PCI bridge
AssigneeInternational Business Machines Corporation
InventorsJonathan Michael Allen, Steven Paul Jones, Daniel Frank Moertl, Adalberto Guillermo Yanes
Life of this patent
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Abstract
Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.
Claims25
A digital system, comprising:
- a bridge;
- a first bus coupled to the bridge;
- a clock generator;
- a first multiplexer coupled to the clock generator, the first bus, and the bridge;
- wherein the first multiplexer is configured to pass one of a first clock signal from the clock generator and a second clock signal from the bridge to the first bus.
A method for clock generation in a digital system, the method comprising:
- providing a first bus coupled to a bridge and a first multiplexer coupled to a clock generator, the first bus, and the bridge;
- and
- passing, by operation of the first multiplexer, one of a first clock signal from the clock generator and a second clock signal from the bridge to the first bus.
A digital system, comprising:
- a bridge;
- N buses coupled to the bridge;
- a clock generator;
- and
- N multiplexers each of which is coupled to the clock generator, the bridge, and one of the N buses, one on one;
- wherein each of the N multiplexers is configured to pass one of a first clock signal from the clock generator and a second clock signal from the bridge to the respective bus.
Dependencies are inferred from the claim text.