Method and apparatus for timing and event processing in wireless systems

A digital baseband processor for concurrent operation with different wireless systems, comprising:

• a digital signal processor for executing digital signal processor instructions;
• a microcontroller for executing microcontroller instructions;
• and
• a timing and event processor controlled by said digital signal processor and said microcontroller for executing timing-sensitive instructions, said timing and event processor comprising:
• a plurality of instruction sequencers for executing timing-sensitive instruction threads;
• and
• a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

A method for generating timing signals for operating a wireless terminal in a wireless system having a wireless system time base, comprising:

• generating a calibrated slow clock;
• generating absolute time values by counting the calibrated slow clock to provide a unified time base;
• and
• timing events in the wireless system based on the absolute time values of the unified time base independent of the wireless system time base.

An apparatus for generating timing signals for operating a wireless terminal in a wireless system having a wireless system time base, comprising:

• means for generating a calibrated slow clock;
• means for generating absolute time values by counting the calibrated slow clock to provide a unified time base;
• and
• means for timing events in the wireless system based on the absolute time values of the unified time base independent of the wireless system time base.

A method for generating a calibrated clock, comprising:

• receiving a free-running fast clock;
• receiving a free-running slow clock;
• modifying the free-running slow clock to provide a calibrated slow clock having a specified frequency relationship to the fast clock;
• and
• providing a phase compensation signal that represents a phase error in the calibrated slow clock.

A method for generating a calibrated clock, comprising:

• receiving a free-running fast clock;
• receiving a free-running slow clock;
• specifying a relationship between the fast clock and a calibrated slow clock;
• counting the number of fast clock cycles in a selected number of free-running slow clock cycles to provide a comparison value;
• removing cycles from the free-running slow clock to provide the calibrated slow clock, based on the specified relationship between the fast clock and the calibrated slow clock, and on the comparison value;
• and
• providing a phase compensation signal that represents a phase error in the calibrated slow clock.

Apparatus for generating a calibrated clock comprising:

• means for receiving a free-running fast clock;
• means for receiving a free-running slow clock;
• means for modifying the free-running slow clock to provide a calibrated slow clock having a specified frequency relationship to the fast clock;
• and
• means for providing a phase compensation signal that represents a phase error in the calibrated slow clock.

A method for performing DMA transfers in a baseband processor, comprising:

• performing computations in a digital signal processor core;
• generating timing signals in a timing and event processor;
• and
• performing a DMA transfer in response to a request from the digital signal processor and in response to the timing signals from the timing and event processor to provide a timed DMA transfer.

A baseband processor for wireless applications, comprising:

• a digital signal processor core for performing digital signal computations;
• a timing and event processor coupled to said digital signal processor core for executing timing-sensitive operations, said timing and event processor comprising a time base generator for generating timing signals, and a DMA control circuit for initiating a DMA request in response to a command from the digital signal processor core and the timing signals from the time base generator;
• and
• a DMA controller for executing the DMA request to provide a timed DMA transfer.