Interface circuit and semiconductor device
OwnerKatsumi Tsukadainventor
Life of this patent
Estimating the term…
Abstract
An interface circuit is provided that shortens the time for which the first CPU cannot use the bus, and minimizes the load on the second CPU. The circuit is equipped with an SRAM that is capable of storing data for one page of the data stored in an SDRAM, and a control section that, upon receiving from a host CPU a page number specifying one of the pages in the SDRAM, transfers to the SRAM data in a page corresponding to the page number; upon receiving from the host CPU a read access request to the data in the SRAM, reads the data requested by the host CPU from the SRAM and transmits the data to the host CPU; and upon receiving from the host CPU a write access request to the data in the SRAM, receives the data transferred by the host CPU and writes the data in the SRAM.
Claims17
An interface circuit that performs data transfer between a first memory that is connected to a first CPU through a bus and stores data divided in a plurality of pages and a second CPU, the interface circuit comprising:
- a second memory adapted to store data for at least one page of the data stored in the first memory;
- and
- a control section that:
- upon receiving from the second CPU page information specifying one of the plurality of pages in the first memory, copies data in the page specified by the page information onto the second memory;
- upon receiving from the second CPU a read access request to data in the second memory, reads the data requested by the second CPU from the second memory and transmits the data to the second CPU;
- and
- upon receiving from the second CPU a write access request to data in the second memory, receives the data transferred by the second CPU and writes the data in the second memory.
A method of performing data transfer between a first memory that is connected to a first CPU through a bus and stores data divided in a plurality of pages and a second CPU with an interface circuit, method comprising:
- in a second memory:
- storing data for at least one page of the data stored in the first memory in a second memory;
- and
- in a control section:
- coping data in the page specified by the page information onto the second memory upon receiving page information specifying one of the plurality of pages in the first memory from the second CPU;
- reading the data requested by the second CPU from the second memory and transmitting the data to the second CPU upon receiving a read access request to data in the second memory from the second CPU;
- and
- receiving the data transferred by the second CPU and writing the data in the second memory upon receiving a write access request to data in the second memory from the second CPU.
Dependencies are inferred from the claim text.