Method of simulation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKenichiro Sonoda
Life of this patent
Estimating the term…
Abstract
A method of simulating a memory transistor is provided. An Id-Vcg characteristic is obtained by actual measurement in Step s2, and an Id-Vfg characteristic is obtained by actual measurement in Step s4. Based on the obtained Id-Vcg and Id-Vfg characteristics, the value of a capacitance (Cfc) for use in circuit simulation of the memory transistor is determined in Step s5. In Step s14, the circuit simulation is performed using the value of the capacitance (Cfc) determined in Step s5. This allows a simulated value to reliably approach a measured value since the determined capacitance (Cfc) is based on a result of actual measurement of the characteristics of the memory transistor.
Claims10
A method of simulating a memory transistor including a control gate, a floating gate, and a substrate having a source region and a drain region formed in a surface thereof, said floating gate and said substrate constituting a MOS transistor structure, said method comprising the steps of:
- (a) preparing said memory transistor;
- (b) obtaining a relationship between a potential of said control gate with respect to said source region and a drain current by actual measurement for said memory transistor;
- (c) preparing a standard transistor having the same structure as said MOS transistor structure of said memory transistor;
- (d) obtaining a relationship between a potential of said floating gate with respect to said source region and a drain current by actual measurement for said standard transistor;
- and
- (e) determining a capacitance value defined between said control gate and said floating gate in said memory transistor for use in a circuit simulation of said memory transistor, based on a result obtained in said step (b) and a result obtained in said step (d),
- wherein the circuit simulation of said memory transistor is performed using said capacitance value determined in said step (e).
A method of simulating a memory transistor including a control gate, a floating gate, and a substrate having a source region and a drain region formed in a surface thereof, said floating gate and said substrate constituting a MOS transistor structure, said method comprising the steps of:
- (a) preparing said memory transistor;
- (b) obtaining a relationship between a threshold voltage and one of the time for which an electron is injected into said floating gate and the time for which an electron is emitted from said floating gate by actual measurement for said memory transistor;
- (c) obtaining a relationship between a gate current flowing between said floating gate and a channel region defined between said source region and said drain region, and a potential of said floating gate with respect to said source region for said memory transistor by using a result obtained in said step (b);
- and
- (d) determining a value of a parameter in a model equation representing said gate current, based on a result obtained in said step (c),
- wherein a circuit simulation of said memory transistor is performed using said model equation in which said value determined in said step (d) is substituted for said parameter.
A method of simulating a memory transistor including a control gate, a floating gate, and a substrate having a source region and a drain region formed in a surface thereof, said memory transistor storing information therein by injection of a hot electron from a channel region defined between said drain region and said source region into said floating gate, said method comprising
- performing a circuit simulation of said memory transistor using a model equation representing a channel electric field at a point of injection of said hot electron into said floating gate in said channel region,
- said model equation being expressed by
- E=(Vd−Vdsat)/lcfor Vfg>Vd−V1, andE=(Vd−Vdsat)/lc×(1−a×(Vd−Vfg−V1)/(Vd+c))for Vfg≦Vd−V1,
- where
- E=the channel electric field at the point of injection of said hot electron into said floating gate in said channel region;
- Vfg=a potential of said floating gate with respect to said source region;
- Vd=a potential of said drain region with respect to said source region;
- Vdsat=a potential of said drain region with respect to said source region at pinchoff;
- and
- V1, 1c, a and c=fitting parameters.
Dependencies are inferred from the claim text.