Method for self-calibrating a phase integration error in a modulator
AssigneeSTMicroelectronics S.r.I.
InventorsGabriele Gandolfi, Andrea Baschirotto, Vittorio Colonna
Life of this patent
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Abstract
A method of self-calibrating a modulator includes at least one integrator likely to incur a phase error may include reading a pulse response of the modulator, calculating a phase error parameter of the at least one integrator, and calibrating the phase error parameter. In addition, the calibration may provide a count of pulse response samples above suitable threshold values, as well as a change in the value of a capacitor associated with the integrator based upon the sample count.
Claims22
A method of self-calibrating a modulator having at least one integrator (23, 24) that is liable to incur a phase error, the method being characterized in that it comprises at least one step of reading a pulse response of said modulator, a step of calculating a phase error parameter (b1, b2) of said integrator, and a step of calibrating said phase error parameter (b1, b2), and in that said calibrating step provides a count (N1) of the pulse response samples lying above suitable threshold values (y1), and a change in the value (Cv) of a capacitor associated with said integrator according to said sample count (N1).
An integrator system with phase error correction, which comprises an integrator (17), having an input terminal (A) connected to an inverting output terminal (B) through a first feedback capacitor (C1), and a second input capacitor (C2) connected between a first input terminal (N+) of said integrator system and said input terminal (A) of said integrator (17), characterized in that it further comprises a phase error correction portion (18) feedback connected between said output terminal (B) and said input terminal (A) of said integrator (17), said correction portion (18) having a variable capacitance value (Cv).
A modulator structure (20) with phase error correction, essentially comprising an oscillation loop (22) connected between an input terminal (IN20) and an output terminal (OUT20), itself including at least first and second integrators (23, 24) and first and second integration coefficients (32, 33) connected between the input terminal (IN20) and said oscillation loop (22), and a feedback coefficient (35) connected between said second integrator (24) and said input terminal (IN20), characterized in that it comprises:
- a first switch block (SW1) connected between said input terminal (IN20) and said first and second integration coefficients (32, 33);
- a second switch block (SW2) connected between said first and second integrators (23, 24);
- a third switch block (SW3) connected between said second integrator (24) and said output terminal (OUT20);
- a fourth switch block (SW4) connected within said feedback loop (22);
- and
- a fifth switch block (SW5) connected between said second integrator (24) and said feedback coefficient (35).
Dependencies are inferred from the claim text.