DC offset cancel circuit
AssigneeFujitsu Limited
InventorShinji Saito
Life of this patent
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AssigneeFujitsu Limited
InventorShinji Saito
Estimating the term…
This invention is applied to dual mode provided receiver capable of coinciding with both TDMA system and the non-TDMA system so as to provide a DC offset cancel circuit preferable for each communication method having a compact structure. In case where a predetermined time slot is allocated as an offset quantity detection time in the TDMA system, a first feedback loop is activated and corresponding to detection signals corresponding to differential output signals OUT, XOUT by a comparator 2, a detection result is updated in the holding section 3 according to a strobe signal STB and held therein. Output signals from the holding section 3 are fed back to an amplifier 1 through a selection section 5 and a DC offset is cancelled out. In case where the offset quantity is detected successively, a second feedback loop is activated and then, detection signals from the comparator 2 are identified by a filter section 4, and fed back to the amplifier 1 through the selection portion 5, so that the DC offset is cancelled out.
A DC offset cancel circuit for canceling DC offset component included in at least one output signal from a signal processing section that applies signal processing to at least one input signal, the DC offset cancel circuit comprising:
Dependencies are inferred from the claim text.