Chip structure and process for forming the same

A chip structure, comprising:

• a substrate having a plurality of electric devices that are disposed on a surface of the substrate;
• a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and an interconnection scheme, the interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the interconnection scheme electrically connected to the electric devices;
• a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the interconnection scheme;
• and
• a second built-up layer arranged over the passivation layer, the second built-up layer provided with at least one power bus, the power bus electrically connected to the interconnection layer with passing through the opening of the passivation layer.

A chip structure, comprising:

• a substrate having a plurality of electric devices that are disposed on a surface of the substrate;
• a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and an interconnection scheme, the interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the interconnection scheme electrically connected to the electric devices;
• a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the interconnection scheme;
• and
• a second built-up layer arranged over the passivation layer, the second built-up layer provided with at least one ground bus, the ground bus electrically connected to the interconnection layer with passing through the opening of the passivation layer.

A chip structure, comprising:

• a substrate having a plurality of electric devices that are disposed on a surface of the substrate;
• a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the dielectric body of the first built-up layer and is electrically connected to the electric devices;
• a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the first interconnection scheme;
• and
• a second built-up layer arranged over the passivation layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected to the first interconnection layer with passing through the opening of the passivation layer, wherein a signal is transmitted from one of the electric devices to the first interconnection scheme, then passes through the passivation layer, and finally is transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme with passing through the passivation layer, and finally is transmitted to the other one or more of the electric devices.

A chip structure, comprising:

• a substrate having a plurality of electric devices that are disposed on a surface of the substrate;
• a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, the first interconnection scheme interlacing inside the dielectric body of the first built-up layer, and the first interconnection scheme electrically connected to the electric devices, the first interconnection scheme including at least one first conductive pad and at least one second conductive pad, and both the first conductive pad and the second conductive pad located on a surface of the first built-up layer;
• a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the first conductive pad and the second conductive pad, and the first conductive pad exposed to the outside;
• and
• a second built-up layer deposited on the passivation layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected with the first interconnection layer through the second conductive pad.

The process for fabricating a chip structure, comprising:

• Step 1:
• providing a wafer with a passivation layer, the passivation layer disposed on a surface layer of the wafer;
• Step 2:
• forming a dielectric sub-layer over the passivation layer of the wafer, the dielectric sub-layer having at least one opening passing through the dielectric sub-layer;
• Step 3:
• forming at least one conductive metal over the dielectric sub-layer and into the opening;
• and
• Step 4:
• removing the conductive metal formed outside the opening.

The process for fabricating a chip structure, comprising:

• Step 1:
• providing a wafer with a passivation layer, the passivation layer disposed on a surface layer of the wafer;
• Step 2:
• forming a first dielectric sub-layer over the passivation layer of the wafer, the first dielectric sub-layer having at least one via metal opening passing through the first dielectric sub-layer;
• Step 3:
• forming a first conductive layer onto the first dielectric sub-layer and into the via metal opening;
• Step 4:
• forming at least one first conductive metal over the first conductive layer;
• Step 5:
• removing the first conductive layer and the first conductive metal that are formed outside the via metal opening.
• Step 6:
• forming a second dielectric sub-layer onto the first dielectric sub-layer, the second dielectric sub-layer having at least one metal-layer opening passing through the second dielectric sub-layer, the metal-layer opening exposing the first conductive metal formed in the via metal opening;
• Step 7:
• forming a second conductive layer onto the second dielectric sub-layer and into the metal-layer opening;
• Step 8:
• forming at least one second conductive metal over the second conductive layer;
• and
• Step 9:
• removing the second conductive layer and the second conductive metal that are formed outside the metal-layer opening.

The process for fabricating a chip structure, comprising:

• Step 1:
• providing a wafer with a passivation layer, the passivation layer disposed on a surface layer of the wafer;
• Step 2:
• forming a first dielectric sub-layer over the passivation layer of the wafer, the first dielectric sub-layer having at least one via metal opening passing through the first dielectric sub-layer;
• Step 3:
• forming a second dielectric sub-layer onto the first dielectric sub-layer and into the via metal opening;
• Step 4:
• removing the second dielectric sub-layer deposited in the via metal opening and at least one part of the second dielectric sub-layer deposited on the first dielectric sub-layer, the removed part of the second dielectric sub-layer outside the via metal opening defining at least one metal-layer opening, the metal-layer opening connecting with the via metal opening;
• Step 5:
• forming a conductive layer onto the second dielectric sub-layer, into the via metal opening and into the metal-layer opening;
• Step 6:
• forming at least one conductive metal over the conductive layer;
• and
• Step 7:
• removing the conductive layer and the conductive metal that are formed outside the metal-layer opening.

A process for forming patterned dielectric sub-layers, a dielectric body of an built-up layer can be constructed from the patterned dielectric sub-layers, the process for forming patterned dielectric sub-layers comprising:

• Step 1:
• providing a first dielectric sub-layer with at least one first opening passing therethrough;
• Step 2:
• forming a second dielectric sub-layer onto the first dielectric sub-layer and into the first opening;
• and
• Step 3:
• removing the second dielectric sub-layer deposited in the via metal opening and at least one part of the second dielectric sub-layer deposited on the first dielectric sub-layer, the removed part of the second dielectric sub-layer outside the via metal opening defining at least one metal-layer opening, the metal-layer opening connecting with the via metal opening.