US 2003/0148587 A1Published application

Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing

AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.

InventorsNorio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda

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Abstract

Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Claims11

Dependent claims

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

(a) providing a semiconductor substrate with a first pattern formed over a first portion of a main surface of said substrate, a second pattern formed over a second portion of said main surface, and a first and a second side wall formed on side surfaces of said first and said second patterns, respectively,
wherein a width of said first side wall is greater than a width of said second side wall;
(b) forming a first groove, in said substrate, in self-alignment with said first side wall and a second groove, in said substrate, in self-alignment with said second side wall;
(c) burying said first and said second grooves with an insulating film;
(d) removing said first and said second patterns;
(e) after said step (d), forming a first insulating film over said first portion and said second portion;
and
(f) after selectively removing said first insulating film formed over said first portion, forming a second insulating film over said second portion such that a thickness of said second insulating film is thinner than a thickness of said first insulating film.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/366,423Filed 14 Feb 2003
Priority: JP 11-0555293 Mar 1999
Published: 7 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/0143
Using trench refilling with dielectric materials, e.g. shallow trench isolations: comprising concurrently refilling multiple trenches having…
H10W 10/0145
Using trench refilling with dielectric materials, e.g. shallow trench isolations: of trenches having shapes other than rectangular or V-shape

Family

Application09/889,018Continuation · filed 10 Jul 2001
Application09/889,018A 371 of international · filed 10 Jul 2001
Application10/366,423Continuation · filed 14 Feb 2003
US 6,562,695 B1Related patent
US 6,720,234 B2Related patent
US 2003/0148587 A1This patent

From the US filing history. Foreign family members aren’t listed.