US 2003/0148583 A1 · Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

Abstract

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Claims33

Dependent claims

A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a semiconductor substrate with first conductor patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;
(b) burying a first insulating film in said grooves;
(c) forming a second conductor pattern over said first conductor patterns and said first insulating film;
(d) forming a second insulating film over said second conductor pattern;
(e) forming a conductive film over said second insulating film;
and
(f) patterning said conductive film, said second conductor pattern and said first conductor patterns in said peripheral circuit region and in said memory cell forming region,
wherein, in said step (f), the conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,
wherein, in said step (f), said second conductor pattern and said first conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (f), at least said second conductor pattern and the first conductor pattern of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.

7 more elements

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;
(b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;
(c) burying a first insulating film in said grooves;
(d) forming a second conductor pattern over said first conductor patterns and said first insulating film;
(e) forming a second insulating film over said second conductor pattern;
(f) forming a second conductive film over said second insulating film;
and
(g) patterning said second conductive film, said second conductor pattern and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,
wherein, in said step (g), said second conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns and said second conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), at least said second conductor pattern and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.

8 more elements

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;
(b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;
(c) burying a first insulating film in said grooves;
(d) forming a second insulating film over said first conductor patterns and said first insulating film;
(e) forming a second conductive film over said second insulating film;
and
(f) patterning said second conductive film and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,
wherein, in said step (f), the second conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,
wherein, in said step (f), said first conductor pattern of said memory cell forming region is patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (f), at least said first conductor pattern of said peripheral circuit region is patterned to form a gate electrode of said MISFET in said peripheral circuit region.

7 more elements

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming first conductor patterns over a memory cell forming region of a semiconductor substrate such that said first conductor patterns cover a peripheral circuit region of said semiconductor substrate;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region such that said grooves serve as an element isolation region in said memory cell forming region;
(c) burying a first insulating film in said grooves by polishing an insulating film deposited over said grooves and said peripheral circuit region;
(d) after said step (c), removing said first conductor patterns from said peripheral circuit region;
(e) after said step (d), forming a conductive film over said first conductor patterns and said peripheral circuit region;
(f) patterning said conductive film and said first conductor patterns in said memory cell forming region and patterning said conductive film in said peripheral circuit region;
and
(g) forming an element isolation region in said peripheral circuit region such that said step (g) is performed in a different manufacturing step from said steps (b) and (c);
wherein, in said step (f), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (f), said first conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (f), said conductive film in said peripheral circuit region is patterned to form a gate electrode of a MISFET of said peripheral circuit region.

8 more elements

A semiconductor device having first MISFETs constituting memory cells, said first MISFETs including a first floating gate electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a control gate electrode formed overlying an upper portion of said first floating gate electrode through an interlayer insulating film, and a pair of semiconductor regions formed in said semiconductor substrate and serving as source/drain regions,

wherein said first MISFETs adjoining in a first direction are isolated by means of a first isolation region having a structure formed by burying a groove of said semiconductor substrate with a first insulating film, said first insulating film having an upper surface higher than said main surface of said semiconductor substrate,
wherein a second floating gate electrode is formed on said upper portion of said first floating gate electrode and is electrically connected with said first floating gate electrode, said interlayer insulating film being formed on said second floating gate electrode, said second floating gate electrode being arranged to extend on said upper surface of said first insulating film, and said upper surface of said first insulating film being higher than said upper portion of said first floating gate electrode,
wherein a first voltage is applied to said control gate electrode during a write operation, and
wherein said first voltage applied to said control gate electrode during the write operation has three or more voltage levels, and changes in threshold level of said first MISFETs logically correspond to said voltage levels on the basis of a difference in amount of charges injected into said first floating gate electrode, whereby information of two bits or more is memorized in one memory cell.

1 more element

Dependencies are inferred from the claim text.

Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

Life of this patent

Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

Life of this patent

Abstract

Claims33