Memory cell fabrication method and memory cell configuration
AssigneeInfineon Technologies AG
InventorsJosef Willer, Veronika Polei
Life of this patent
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Abstract
The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.
Claims7
A method of fabricating an EEPROM memory cell, which comprises:
- forming a source region and a drain region, with a channel region therebetween, in semiconductor material;
- and
- applying a three-layered layer structure with a storage layer between boundary layers and a gate electrode above the channel region, by performing the following steps:
- in a first step, applying on a top side of a semiconductor material a first boundary layer, an etching layer, a second boundary layer, and a gate electrode, whereby a material of the etching layer is selectively etchable with respect to a material of the first boundary layer and a material of the second boundary layer;
- in a second step, removing at least the second boundary layer and the etching layer outside a region provided for the memory cell;
- in a third step, selectively removing portions of the etching layer by a laterally effected etching attack under the second boundary layer, to form of the etching layer a residual portion above the channel region between the source region and the drain region;
- in a fourth step, filling at least those regions below the second boundary layer wherein the material of the etching layer was removed with a material for a storage layer;
- and
- subsequently processing further method steps for electrically connecting the resulting memory cell.
A memory cell of an EEPROM, comprising:
- a semiconductor material having a source region and a drain region formed therein;
- a channel region between said source region and said drain region;
- a three-layered layer structure formed above said channel region and a gate electrode above said layer structure, said layer structure having boundary layers and a storage layer between said boundary layer;
- and
- an interruption of said storage layer above said channel region formed of a region of Al2O3 between said boundary layers.
Dependencies are inferred from the claim text.