US 2003/0148579 A1Published application

Semiconductor device and method of manufacturing the same

AssigneeFujitsu Limited

InventorsYukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai

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Abstract

There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.

Claims8

Dependent claims

A method of manufacturing a semiconductor device comprising the steps of:

forming a transistor having a first impurity diffusion layer and a second impurity diffusion layer formed in a semiconductor substrate and an electrode formed above the semiconductor substrate;
forming a first insulating film to cover the transistor;
forming a first conductive film, a ferroelectric or high-dielectric film, and a second conductive film in sequence above the first insulating film;
forming an upper electrode of a capacitor by patterning the second conductive film;
forming a dielectric film of the capacitor by patterning the ferroelectric or high-dielectric film;
forming a first capacitor protection film to cover the upper electrode and the dielectric film;
leaving the first capacitor protection film on at least the upper electrode and the dielectric film;
forming a lower electrode of the capacitor by patterning the first conductive film;
forming a second insulating film above the first insulating film and the first capacitor protection film;
forming a first hole on the upper electrode by patterning the first protection film and the second insulating film;
forming a second hole above the first impurity diffusion layer by patterning the first insulating film and the second insulating film;
forming a first wiring, that electrically connects the upper electrode and the first impurity diffusion layer via the first hole and the second hole, above the second insulating film;
forming a second capacitor protection film over the first wiring and the second insulating film to cover at least the capacitor;
forming a third insulating film to cover the second capacitor protection film;
and
forming a second wiring over the third insulating film.

13 more elements

A method of manufacturing a semiconductor device comprising the steps of:

forming a transistor having a first impurity diffusion layer and a second impurity diffusion layer formed in a semiconductor substrate and an electrode formed above the semiconductor substrate;
forming a first insulating film to cover the transistor;
forming a first conductive film, a ferroelectric or high-dielectric film, and a second conductive film in sequence above the first insulating film;
forming an upper electrode of a capacitor by patterning the second conductive film;
forming a dielectric film of the capacitor by patterning the ferroelectric or high-dielectric film;
forming a first capacitor protection film to cover the upper electrode and the dielectric film;
leaving the first capacitor protection film on at least the upper electrode and the dielectric film;
forming a lower electrode of the capacitor by patterning the first conductive film;
forming a second insulating film above the first insulating film and the first capacitor protection film;
forming a first hole on the upper electrode by patterning the first protection film and the second insulating film;
forming a second hole above the first impurity diffusion layer by patterning the first insulating film and the second insulating film;
forming a first wiring, that electrically connects the upper electrode and the first impurity diffusion layer via the first hole and the second hole, above the second insulating film;
forming a third insulating film to cover the first wiring;
forming a ground hole at a side region of the capacitor by patterning the first and second and third insulating films;
forming a second wiring above the third insulating film;
forming a ground wiring above the third insulating film, the ground wiring connected electrically to the semiconductor substrate via the ground hole;
forming a fourth insulating film above the third insulating film to cover the second wiring and the ground wiring;
and
forming a second capacitor protection film formed of a conductive film above the fourth insulating film and over at least the capacitor, the second capacitor protection film connected electrically to the ground wiring.

16 more elements

A method of manufacturing a semiconductor device comprising the steps of:

forming a transistor having a first impurity diffusion layer and a second impurity diffusion layer formed in a semiconductor substrate and an electrode formed above the semiconductor substrate;
forming a first insulating film to cover the transistor;
forming a first conductive film, a ferroelectric or high-dielectric film, and a second conductive film in sequence above the first insulating film;
forming an upper electrode of a capacitor by patterning the second conductive film;
forming a dielectric film of the capacitor by patterning the ferroelectric or high-dielectric film;
forming a first capacitor protection film to cover the upper electrode and the dielectric film;
leaving the first capacitor protection film on at least the upper electrode and the dielectric film;
forming a lower electrode of the capacitor by patterning the first conductive film;
forming a second insulating film above the first insulating film and the first capacitor protection film;
forming a first hole on the upper electrode by patterning the first protection film and the second insulating film;
forming a second hole above the first impurity diffusion layer by patterning the first insulating film and the second insulating film;
forming a first wiring, that electrically connects the upper electrode and the first impurity diffusion layer via the first hole and the second hole, above the second insulating film;
forming a second capacitor protection film over the first wiring and the second insulating film to cover at least the capacitor;
forming a third insulating film to cover the second capacitor protection film;
forming a ground hole at a side region of the capacitor by patterning the first insulating film, the second insulating film, and the third insulating film;
forming a second wiring above the third insulating film;
forming a ground wiring above the third insulating film, the ground wiring connected electrically to the semiconductor substrate via the ground hole;
forming a fourth insulating film above the third insulating film to cover the second wiring and the ground wiring;
forming a third conductive film above the fourth insulating film;
forming a third capacitor protection film above the fourth insulating film and over at least the capacitor by patterning the third conductive film, the third capacitor protection film connected electrically to the ground wiring;
and
forming a third wiring by patterning the third conductive film.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/361,585Filed 11 Feb 2003
Priority: JP 2000-28273018 Sep 2000
Published: 7 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 53/00
Ferroelectric ram [feram] devices comprising ferroelectric memory capacitors
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10D 1/682
Capacitors having no potential barriers: having dielectrics comprising perovskite structures
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells

Family

Application09/819,738Division · filed 29 Mar 2001
Application10/361,585Division · filed 11 Feb 2003
US 2002/0061620 A1Published application
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US 2003/0148579 A1This patent

From the US filing history. Foreign family members aren’t listed.