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AssigneeRenesas Technology Corp.
InventorsMasaharu Kubo, Ichiro Anjo, Akira Nagai, Osamu Kubo, Hiromi Abe, Hitoshi Akamine
Estimating the term…
CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.
A semiconductor integrated circuit device having an integrated circuit including a plurality of semiconductor elements and a plurality of wirings formed on a plurality of wiring layers,
A method of manufacturing a semiconductor integrated circuit having an integrated circuit by carrying out a plurality of steps, characterized by dividing the plurality of steps into a plurality of step groups, realizing the plurality of step groups on different types of plural substrates, and electrically connecting the plural substrates with one another to manufacture said integrated circuit.
A method of manufacturing a semiconductor integrated circuit having an integrated circuit device by carrying out a plurality of steps, characterized by comprising the steps of:
A semiconductor integrated circuit device, characterized by comprising a glass substrate having a main surface and a back surface, multi-layered wirings formed on the main surface of said glass substrate, first plural connection terminals formed on the back surface of said glass substrate, a plurality of semiconductor chips each having a main surface, and second plural connection terminals formed on the respective main surfaces of the plurality of semiconductor chips, wherein the main surfaces of said plurality of semiconductor chips are arranged in face-to-face relation with the main surface of said glass substrate, and at least some of second plural connection terminals are electrically connected to said first plural connection terminals via said multi-layered wirings.
A semiconductor integrated circuit device, characterized by comprising a glass substrate having a main surface and a back surface, multi-layered wirings formed on the main surface of said glass substrate, first plural connection terminals formed on the back surface of said glass substrate, a semiconductor chip having a main surface, and second plural connection terminals formed on the main surface of said semiconductor chip, wherein the main surface of said semiconductor chip is arranged in face-to-face relation with the main surface of said glass substrate, and at least some of said second plural connection terminals are electrically connected to said first plural connection terminals via said multilayered wirings.
Dependencies are inferred from the claim text.