Back to results
US 2003/0148077 A1Published application
High-performance laminate for integrated circuit interconnection
AssigneeAgilent Technologies, Inc.
InventorsNurwati S. Devnani, William S. Burton, Sari K. Christensen
Life of this patent
Estimating the term…
Abstract
A high-performance, integrated circuit interconnection laminate. Power/ground layers in laminates fabricated with open areas to permit out gassing of gases generated during high temperature lamination are located such that they do not lie under/over critical traces on signal layers. This placement of the open areas enables a reduction in cross-talk between signal layers lying on opposite sides of a power/ground layer and a reduction in signal delay.
Claims11
A laminate for interconnecting an integrated circuit chip, which comprises:
- a first layer, wherein the first layer comprises an electrically conducting area and multiple open areas, wherein centroids of two of the open areas define one axis of a Cartesian coordinate system, and wherein the open areas are interspersed inside an outer perimeter of the electrically conducting area;
- a second layer, wherein the second layer is electrically insulating, wherein the second layer overlays the first layer;
- and
- a third layer, wherein the third layer comprises multiple electrically conducting traces, wherein the third layer overlays the second layer, wherein at least one of the traces is oriented at other than an orthogonal angle to each axis of the coordinate system, wherein the oriented trace is longer than the spatial extension between two of the open areas, and wherein the projection of the oriented conducting trace onto the first layer lies external to the open areas.
1 more element
Dependencies are inferred from the claim text.