US 2003/0147482 A1 · Single ended termination of clock for dual link DVI receiver

Abstract

A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Claims42

Dependent claims

A receiver that receives high rate bit stream data, the receiver comprising:

a plurality of data buffers, each of which couples to a transmission path carrying a respective high rate serial bit stream, wherein each of the plurality of data buffers includes:
an input that receives the respective high rate serial bit stream;
buffering circuitry that buffers the respective high rate serial bit stream;
and
an output that produces a buffered representation of the respective high rate serial bit stream;
a clock buffer that receives and buffers a clock signal corresponding to the high rate bit stream data and includes:
an input that receives the clock signal;
buffering circuitry that buffers the clock signal;
and
an output that produces a buffered representation of the clock signal;
and
clock termination circuitry coupled to a transmission path that carries the clock signal, wherein the clock termination circuitry applies a terminating impedance to the transmission path that carries the clock signal during a first operating condition, and wherein the clock termination circuitry applies a high impedance to the transmission path that carries the clock signal during a second operating condition.

9 more elements

A receiver that terminates a dual link digital interface, wherein each link of the dual link digital interface comprises a plurality of data channels, and wherein both of the dual links are serviced by a common clock signal, the receiver comprising:

a first link receiver that comprises;
a first set of data buffers, each of which terminates a corresponding data channel of the first link and buffers data received there on;
and
first clock termination circuitry coupled to a transmission path that carries the clock signal, wherein the clock termination circuitry applies a terminating impedance to the transmission path that carries the common clock signal during a first operating condition, and wherein the clock termination circuitry applies a high impedance to the transmission path that carries the common clock signal during a second operating condition;
and
a second link receiver that comprises;
a second set of data buffers, each of which terminates a corresponding data channel of the second link and buffers data received there on;
and
second clock termination circuitry coupled to a transmission path that carries the clock signal, wherein the clock termination circuitry applies a high impedance to the transmission path that carries the common clock signal during the first operating condition, and wherein the clock termination circuitry applies a terminating impedance to the transmission path that carries the common clock signal during a second operating condition.

6 more elements

Dependencies are inferred from the claim text.

Single ended termination of clock for dual link DVI receiver

Life of this patent

Single ended termination of clock for dual link DVI receiver

Life of this patent

Abstract

Claims42