Data transfer interface for a switching network and a test method for said network
OwnerKarsten Laubner, Franz Lindwurm +1inventors
InventorsKarsten Laubner, Franz Lindwurm, Marcel-Abraham Troost
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Abstract
The invention relates to a data transfer interface for a switching network and to a test method for said network. According to the invention, a plurality of test channels (syn0 bis syn3, asw0 bis asw9, tstch) are included in a synchronous time-division multiplex frame comprising a plurality of payload channels (payld). In addition, each channel has additional test bits. A secure data transfer interface is thus obtained, which can be used for online monitoring.
Claims9
A data communication interface for a switching network comprising
- a synchronous time-division multiplex frame for accommodating a multiplicity of data channels, wherein the data channels of the synchronous time-division multiplex frame consist of a multiplicity of payload channels (payld) and test channels (syn0 to syn3, asw0 to asw9, tstch) and are expanded by additional test bits (parity0, parity1), characterized in that some of the test channels (asw0 to asw9) are used for memory address supervision, wherein
- a channel number of the test channels (asw0 to asw9) for memory address supervision is selected in such a manner that in each case only one address bit of respective memory addresses has the value “1”.
A method for testing a switching network comprising a multiplicity of time-division switching units (ZK) and space-division switching units (RK), consisting of the following steps:
- a) expanding payload and test channels by additional test bits (parity0, parity1);
- b) determining a test sum of data bits of the respective data channels to be transmitted and correspondingly specifying the test bits;
- c) transmitting the test bits and the data bits in the respective data channels;
- d) determining a test sum of the transmitted data bits;
- and
- e) evaluating the test sum determined and the test bits transmitted in order to detect errors,
- wherein
- channel numbers of test channels (asw0 to asw9) for memory address supervision are selected in such a manner that only one predetermined address in which only one address bit in each case of respective memory addresses has the value “1”, of a time-division and/or space-division switching unit (ZK, RK) is described, and a corresponding data channel content is checked for correspondence at a downstream time-division and/or space-division switching unit.
Dependencies are inferred from the claim text.