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US 2003/0147398 A9Published application
Packet switch
AssigneeFujitsu Limited
InventorsNaoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
Life of this patent
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Abstract
A packet switch which can cyclically use α scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by α scheduler sections independently performing scheduling processes is disclosed.
Claims12
A packet switch, comprising:
- N input buffer sections, provided corresponding to n input lines, for storing a packet input through the corresponding input lines;
- α scheduler sections for determining one of m output lines as a destination of the packet stored in each of said n input buffer sections by a scheduling process independently performed by each scheduler section;
- and
- a switch section for outputting the packet output from each of said n input buffer sections to the destination output line determined by said scheduler section,
- wherein said n input buffer sections cyclically use results of scheduling processes by said α scheduler sections.
2 more elements
Dependencies are inferred from the claim text.