Semiconductor memory device capable of making switch between synchronizing signals for operation on data generated by different circuit configurations

A semiconductor memory device inputting/outputting data to/from memory cells in synchronism with a rise and a fall of a synchronizing signal, comprising:

• a plurality of memory cells;
• a synchronizing signal generating circuit receiving first and second synchronizing signals, generating a first internal synchronizing signal on the basis of said first synchronizing signal, generating a second internal synchronizing signal on the basis of said second synchronizing signal, and generating a third internal synchronizing signal by means of the same circuit configuration as a circuit generating one of said first and second internal synchronizing signals on the basis of one of said first and second synchronizing signal;
• a peripheral circuit inputting/outputting data to/from each of said plurality of memory cells in synchronism with said rise and said fall of said second internal synchronizing signal;
• and
• an input circuit receiving data inputted externally in synchronism with said first synchronizing signal, latching the received data sequentially in synchronism with said first internal synchronizing signal, said third internal synchronizing signal and said second internal synchronizing signal to output the latched data to said peripheral circuit.