Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system

A synchronous semiconductor memory device for receiving an address signal and a control signal in synchronization with an external clock signal, comprising:

• a control circuit for controlling an operation of said synchronous semiconductor memory device;
• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a first internal synchronous signal generating circuit for generating a first internal clock signal synchronized with said external clock signal;
• a control signal input circuit for receiving said address signal and said control signal;
• a memory cell select circuit for selecting said memory cell in accordance with said address signal;
• a plurality of data I/O nodes for receiving data for transmission to and from said memory cells;
• and
• a plurality of interface circuits arranged between said memory cells selected by said select circuit and said data I/O nodes for transmitting said write data, respectively,
• each of said interface circuits including:
• a first latch circuit controlled by said control circuit to receive and hold, in synchronization with said first internal clock signal, the plurality of data applied in time series to the corresponding I/O node, and to send said held data to the selected memory cells as parallel data,
• a second latch circuit controlled by said control circuit to receive and hold said plurality of data read out from the selected memory cells, and to convert said held data into time-series data in synchronization with said first internal clock signal for applying said time-series data to the corresponding I/O node, and
• a transfer circuit controlled in the write operation by said control circuit for transferring the data held in said first latch circuit to said second latch circuit;
• and
• said control circuit converting the data transferred to and held in said second latch circuit into time-series data in synchronization with said first internal clock signal, and applying said time-series data to the corresponding I/O node when said control circuit receives an instruction for the read operation and a read address matching with an address applied in the immediately preceding read operation or the immediately preceding write operation.

A synchronous semiconductor memory device for receiving an address signal and a control signal based on mutually complementary first and second external clock signals comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns,
• said memory cell array including a plurality of memory cell blocks:
• a control circuit for controlling an operation of said synchronous semiconductor memory device in synchronization with said first and second external clock signals;
• a memory cell select circuit provided correspondingly to each of said memory cell blocks for selecting the plurality of memory cells at a time in accordance with said address signal;
• and
• a plurality of data I/O nodes for receiving read data read from said memory cells:
• and
• an interface circuit arranged between the memory cells selected by said memory cell select circuit and said data I/O nodes for transmitting said read data,
• said interface circuit including:
• a plurality of holding circuit pairs provided correspondingly to the pairs of said memory cell blocks, respectively, for holding the read data read from said plurality of memory cells, and
• a data I/O circuit for applying the read data held in said holding circuit pairs alternately to the corresponding data I/O nodes in synchronization with activation edges of said first and second external clock signals in a first operation mode, and applying the read data held in one of said paired holding circuits to the corresponding data I/O node in synchronization with one of said first and second external clock signals in a second operation mode.