Autotesting method of a memory cell matrix, particularly of the non-volatile type
AssigneeSTMicroelectronics S.r.I.
InventorsAntonino Geraci, Alberto Campisi, Lorenzo Bedarida, Simone Bartoli
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AssigneeSTMicroelectronics S.r.I.
InventorsAntonino Geraci, Alberto Campisi, Lorenzo Bedarida, Simone Bartoli
Estimating the term…
An autotesting method of a cells matrix of a memory device is disclosed which comprises the steps of: reading the values contained in a plurality of the memory cells; comparing the read values with reference values; signalling mismatch of the read values with the reference values as an error situation; and storing the error situations. In the autotesting method, the reading, comparing, signalling, and storing steps are repeated for all the memory cells in an matrix column. The autotesting method according to the invention further comprises the steps of storing the positions of any columns having at least one one error situation; and repeating all of the preceding steps according to a step of scanning all the matrix columns.
An autotesting method of a cells matrix of a memory device, characterized in that it comprises the steps of:
An autotesting method according to claim 1, characterized in that said error situations are stored into the same memory area of said memory device.6. An autotesting method according to claim 5, characterized in that said a high logic value stored in said memory area is an indication of a column having at least one error situation.
A memory device, of the type which comprises at least one matrix of memory cells connected to a plurality of sense amplifiers adapted to output on output buses values contained in said memory cells, characterized in that it comprises an autotesting architecture connected between said output buses of said plurality of sense amplifiers and a plurality of output terminals of said memory device and adapted to compare said read values with corresponding reference values to locate and signal any mismatches as error situations on said plurality of output terminals.
A method for testing of memory cells within a memory matrix, wherein the matrix comprises memory cells arranged in subsets of memory cells, the method comprising:
A method, comprising:
A memory, comprising:
Dependencies are inferred from the claim text.