High data rate serial ferroelectric memory
OwnerMary E. Hackbarth, Rodney W. Roark +2inventors
InventorsMary E. Hackbarth, Rodney W. Roark, Donald J. Verhaeghe, Dennis C. Young
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Abstract
A method for accessing data in a serial ferroelectric memory device including an input shift register coupled to a ferroelectric memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the memory array having associated row, column, and segment decoders, includes clocking a serial address into the input shift register and starting a read access before the serial address is completely shifted into the input shift register. A read access can be started before an input bit sequence containing row, column, and segment decoder addresses has been completely clocked into the memory.
Claims22
A method for accessing data in a serial memory device including an N-bit input shift register coupled to a memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the method comprising:
- clocking an N-bit bit sequence into the input shift register;
- and
- starting a read access when an (N−M)th address bit is shifted into the input shift register.
A method for accessing data in a serial memory device including an input shift register coupled to a memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the method comprising:
- clocking a serial address into the input shift register;
- and
- starting a read access before the serial address is completely shifted into the input shift register.
A method of operating a serial ferroelectric memory comprising starting a read access before an input bit sequence containing row and column addresses has been completely clocked into the memory.
Dependencies are inferred from the claim text.