Nonvolatile semiconductor memory with power-up read mode
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Keun Lee
Life of this patent
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Abstract
A nonvolatile semiconductor memory device executing an automatic read operation at the time of a power-up is disclosed. For the automatic read operation, it starts to generate a wordline voltage when a power supply voltage at a power-up time reaches a first voltage. When the wordline voltage is charged up to a desired voltage level, a read operation begins automatically.
Claims22
A nonvolatile semiconductor memory comprising:
- an array of memory cells arranged in a matrix of rows and columns;
- a voltage detector for activating a first detection signal when a power supply voltage reaches a first detection voltage during a power-up phase;
- a read voltage generator for creating a read voltage in response to the first detection signal and for activating a second detection signal when the read voltage reaches a second detection voltage;
- a read start signal generator for generating a read start signal in response to an activation of the second detection signal;
- and
- read circuitry for reading data from the memory cell array in response to the read start signal.
A nonvolatile semiconductor memory comprising:
- an array of memory cells arranged in a matrix of rows and columns;
- a first voltage detector for activating a first detection signal when a power supply voltage reaches a first detection voltage at a power-up time;
- a read voltage generator for creating a read voltage in response to the first detection signal and for activating a second detection signal when the read voltage reaches a second detection voltage;
- a row decoder for selecting one of the rows in response to a row address, and for transferring the read voltage to the selected row;
- a column decoder for selecting a part of the columns in response to column addresses;
- a read start signal generator for generating a read start signal in response to an activation of the second detection signal;
- a sensing circuit for reading data from the memory cells designated by the selected rows and columns;
- and
- a read controller for operating the sensing circuit in response to the read start signal.
A nonvolatile semiconductor memory operable in a power-up read mode, comprising:
- an array of memory cells arranged in a matrix of rows and columns;
- a first voltage detector for activating a first detection signal when a power supply voltage reaches a first detection voltage in a power-up phase;
- an address buffer for receiving an external address;
- a read voltage generator for creating a read voltage in response to the first detection signal and for activating a second detection signal when the read voltage reaches a second detection voltage;
- a row decoder for selecting one of the rows in response to a row address among the external address and for transferring the read voltage to the selected row;
- a column decoder for selecting a part of the columns in response to column addresses among the external address;
- a sensing circuit for reading data from memory cells designated by the selected row and columns;
- a flipflop structured to be reset by the first detection signal and set by the second selection signal;
- a read start signal generator for generating a read start signal when the flipflop is set by an activation of the second detection signal;
- and
- a read controller for operating the sensing circuit in response to the read start signal.
A method for power-up reading in a nonvolatile memory, the method comprising:
- activating a first detection signal when a power supply voltage reaches a first detection voltage in a power-up phase;
- generating a wordline voltage in response to an activation of the first detection signal;
- determining when the wordline voltage reaches a second detection voltage;
- and
- conducting a read operation for the memory when the wordline voltage reaches the second detection voltage.
Dependencies are inferred from the claim text.