Nonvolatile memory device and refreshing method
AssigneeRenesas Technology Corp.
InventorsHitoshi Miwa, Hiroaki Kotani
Life of this patent
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Abstract
At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.
Claims7
A nonvolatile memory device in which data of two bits or more are stored in one memory cell by setting the threshold value of said memory cell to two or more stages and by changing the level of a word line to two or more stages to read said memory cell, comprising:
- a binary data register for latching program data inputted;
- a data transforming logic circuit for executing a predetermined operation of a plurality of bits of the input data to transform said input data into multi-value data according to their combination;
- and an inverse transforming logic circuit for transforming the multi-value data read out from said memory cell into the original binary data.
A control device connected to a nonvolatile memory device in which data of two bits or more are stored in one memory by setting the threshold value of said memory cell to two or more stages and by changing the level of a word line to two or more stages to read said memory cell, comprising:
- a binary data register for latching program data;
- a data transforming logic circuit for executing a predetermined operation of a plurality of bits of the input data to transform said input data into multi-value data according to their combination;
- and an inverse transforming logic circuit for transforming the multi-value data read out from said nonvolatile memory device into the original binary data.
A method for refreshing a nonvolatile memory device in which data of two bits or more are stored in one memory cell by setting the threshold value of said memory cell to two or more stages and by changing the level of a word line to two or more stages to read said memory cell, wherein a threshold value is raised by applying a weak erase pulse to all the memory cells, and wherein a program pulse is then applied to memory cells whose threshold values are excessively raised, on the basis of the data read out by a predetermined word line voltage, thereby to reduce the variation of the threshold values.
Dependencies are inferred from the claim text.