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US 2003/0147280 A1Published application
Memory device with multi-level storage cells
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
Estimating the term…
Abstract
The present invention comprises memory devices, including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.
Claims9
A method of operating a multiple bit per cell memory device comprising:
- providing said multiple bit per cell memory device with x multiple bit per cell memory cells, each with y states;
- applying power to said multiple bit per cell memory device;
- running a self-test on each of yx possible states of said multiple bit per cell memory device to identify z faulty states, wherein z≧0;
- assigning a unique state to each of yx - z working states of said multiple bit per cell memory device;
- mapping each assigned unique state to a unique binary state of n binary bits, where 2n<yx and n is an integer;
- and
- designating yx - z - 2n spare states as invalid data states.
4 more elements
A method of operating a multiple bit per cell memory device comprising:
- providing said multiple bit per cell memory device with x multiple bit per cell memory cells, each with y states;
- applying power to said multiple bit per cell memory device;
- running a self-test on each of yx possible states of said multiple bit per cell memory device to identify z faulty states, wherein z≧0;
- assigning a unique state to each of yx - z working states of said multiple bit per cell memory device;
- mapping each assigned unique state to a unique binary state of n binary bits, where 2n<yx and n is an integer;
- and
- designating yx - z - 2n spare states.
4 more elements
A method of erasing data in a multiple bit per cell memory device comprising:
- providing said multiple bit per cell memory device with x multiple bit per cell memory cells, each with y states;
- assigning a unique state to each of yx possible states of said multiple bit per cell memory device;
- mapping each assigned unique state to a unique binary state of n binary bits, where 2n<yx and n is an integer;
- utilizing at least one of yx - 2n spare states for indicating erased memory cells;
- reading each of said indicated erased memory cells to determine whether it is erased or not erased;
- and
- erasing each of said indicated erased memory cells only if it is not erased.
4 more elements
Dependencies are inferred from the claim text.