Suppression of leakage currents in VLSI logic and memory circuits

Abstract

An SRAM system is provided having an array of SRAM cells receiving a first power voltage. The SRAM system includes at least one circuit receiving a first power voltage, and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit of the system. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. Furthermore, a method is provided for providing a power supply voltage to at least one circuit of a system. The method includes the steps of providing a first power supply voltage to the at least one circuit of the system, and providing a second power supply voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system, and the at least one selected circuit is one of a selected memory cell, a sense amplifier and a critical path of the logic system.

Dependencies are inferred from the claim text.