Uni-transistor random access memory device and control method thereof

A method of controlling operations of a static random access memory, comprising:

• charging a first bitline coupled to a first cell transistor and a second bitline coupled to a second cell transistor to a first voltage;
• activating a wordline commonly coupled to the first and second cell transistors;
• sensing and amplifying a difference between voltage on the first bitline and voltage on the second bitline;
• transferring amplified voltages on the first and second bitlines to corresponding input/output lines;
• and
• inactivating an activated wordline when the voltage on one of the first and second bitlines is substantially the same as a second voltage,
• wherein the first voltage is a power supply voltage for an array and the second voltage is a ground voltage.

A static random access memory comprising:

• a plurality of twin cells each having a first memory cell and a second memory cell, the twin cells being arranged in a matrix of rows and columns;
• a row selection circuit for activating one of the rows in response to a row address;
• a bitline precharge circuit for charging first and second bitlines of each column to a power supply voltage in response to a precharge control signal;
• and
• a sense amplifier circuit for sensing and amplifying a voltage difference between the first and second bitlines of each column,
• wherein the row selection circuit inactivates the activated row when a voltage on one of the first and second bitlines of each column reaches a ground voltage.