Method and apparatus for sensing resistance values of memory cells
AssigneeMicron Technology, Inc.
InventorR. Jacob Baker
Life of this patent
Estimating the term…
Abstract
A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).
Claims60
A method for sensing resistance of cells of a memory array, the method comprising:
- passing a current through each of a plurality of resistors associated with unselected memory cells of said memory array;
- passing said current through a resistor associated with a selected memory cell of said memory array;
- and
- measuring a voltage drop across said resistor associated with said selected memory cell to determine a resistance value of said resistor.
A circuit for sensing resistance of cells of a memory array, the circuit comprising:
- a plurality of resistors associated with said memory array such that when a memory cell of said array is selected, said plurality of resistors, except for a resistor associated with said selected memory cell, are connected in parallel, said resistor associated with said selected memory cell being in series with said plurality of resistors connected in parallel;
- and
- a current source coupled to said memory array for driving a current through said plurality of resistors connected in parallel and said resistor associated with said selected memory cell.
A circuit for sensing resistance of cells of a memory array, the circuit comprising:
- a plurality of resistors associated with said memory array such that when a memory cell of said array is selected, the plurality of resistors, except for a resistor associated with said selected memory cell, is connected to form a first equivalent resistance, said resistor associated with said selected memory cell being in series with said first equivalent resistance;
- and
- a current source coupled to said memory array for driving a current through said first equivalent resistance and said resistor associated with said selected memory cell.
A control system for sensing resistance of cells of a memory array, the system comprising:
- a memory array comprising a plurality of resistors, each of said resistors corresponding to a memory cell of said array;
- a current source coupled to said memory array for passing a current through said plurality of resistors;
- and
- a monitor for monitoring a voltage level measured across at least a selected one of said plurality of resistors in said memory array, such that if said voltage level deviates from a predetermined value, said current is adjustable.
A control system for sensing resistance of cells of a memory array, the system comprising:
- a memory array comprising a plurality of resistors, each of said resistors corresponding to a memory cell of said memory array;
- a current source coupled to said memory array for passing a current through said plurality of resistors associated with memory cells;
- and
- a current limiting device coupled between said current source and said memory array for limiting said current to said memory array.
A memory array comprising:
- a first reference cell containing a first resistor of a first resistance value;
- a second reference cell containing a second resistor of a second resistance value, wherein a current source is coupled to said first and second reference cells for passing a current through said first and second reference cells, and wherein
- said first and second reference cells are coupled to each other so as to enable a detection of a reference voltage to be fed into an input of a comparator for comparing said reference voltage with a voltage sensed from a selected memory cell of said memory array.
Dependencies are inferred from the claim text.