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US 2003/0147269 A1Published application
Memory device and memory system using same
AssigneeSony Corporation
InventorToshiyuki Nishihara
Life of this patent
Estimating the term…
Abstract
A memory device including a cross point type ferroelectric memory and a randomly accessible write back type cache memory, where the cross point type ferroelectric memory is accessed via a second memory, and a memory system using the same. By this, data in the cache memory can be freely randomly accessed, the cross point type memory is accessed only at miss hits, and the number of data rewrites is greatly reduced.
Claims15
A memory system having a first memory and a second memory, wherein
- the first memory has:
- at least one bit line,
- at least one word line,
- a plurality of plate lines, and
- and at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines;
- the second memory includes a random accessible write back type cache memory;
- and
- the first memory is accessed via the second memory.
5 more elements
A memory device comprising:
- at least one bit line;
- at least one word line;
- a plurality of plate lines;
- and
- at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines;
- and
- having the function of omitting a re-storage of data into an accessed ferroelectric capacitor when reading data.
4 more elements
A memory device having a first memory region and a second memory region, wherein:
- the first memory region has:
- at least one bit line,
- at least one word line,
- a plurality of plate lines, and
- at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines;
- and
- the second memory region:
- includes a random accessible memory connected to the same bit line as that for the first memory region and
- has the function of transferring at least part of the data from the first memory region to the second memory region.
6 more elements
Dependencies are inferred from the claim text.