Method and structure for reduction of impedance using decoupling capacitor

A structure for reducing stray inductance in a circuit comprising:

• a printed circuit board having first and second opposite faces and at least two voltage planes, and vias extending from each of said faces to one of said voltage planes,
• an I/C chip structure having at least one active device thereon, connectors connecting said active devices on said I/C chip structure to said vias on one face of said printed circuit board,
• a discrete decoupling capacitor structure comprising at least two interlaced conductive plates in dielectric material forming at least one capacitor connected to the other face of said printed circuit board,
• vias extending from each of said conductive plates through said dielectric material to connect each via to a circuit board via on said second face of said printed circuit board,
• said vias in said decoupling capacitor structure being configured and arranged such that the vias are parallel to each other, and each via connected to one conductive plate is located adjacent a via connected to another conductive plate.

A structure for reducing stray inductance in a circuit comprising:

• a printed circuit board having first and second opposite faces and at least two voltage planes, and vias extending from said one face to one of said voltage planes,
• an I/C chip structure having first and second faces, and having at least one active device thereon, connectors connecting said active devices on said I/C chip structure through said first face of said I/C chip structure to said circuit board vias on said one face of said printed circuit board,
• a discrete decoupling capacitor structure comprising at least two interlaced conductive plates in dielectric material forming at least one capacitor connected to said conductive plates of said I/C chip structure through said second face of said I/C chip structure,
• vias extending from each of said conductive plates through said dielectric material to connect each via to a connector on said second face of said I/C chip structure,
• said vias in said decoupling capacitor structure being configured and arranged such that the vias are parallel to each other, and each via connected to one conductive plate is located adjacent a via connected to another conductive plate.

A method for reducing stray inductance in a circuit comprising the steps of:

• providing a printed circuit board having first and second opposite faces and at least two voltage planes, and vias extending from each of said faces to one of said voltage planes,
• providing an I/C chip structure having at least one active device thereon;
• connectors connecting said active devices on said I/C chip structure to said conductors on one face of said printed circuit board,
• providing a discrete decoupling capacitor structure comprising at least two interlaced conductive plates in dielectric material forming at least one capacitor, vias extending from each of said conductive plates through said dielectric material, said vias in said decoupling capacitor structure being configured and arranged such that the vias are parallel to each other, and each via connected to one conductive plate is located adjacent a via connected to another conductive plate, and
• connecting each circuit board via to a decoupling capacitor on said second face of said printed circuit board.

A method for reducing stray inductance in a circuit comprising the steps of:

• providing a printed circuit board having first and second opposite faces and at least two voltage planes, and vias extending from said one face to one of said voltage planes,
• providing an I/C chip structure having first and second faces, and having at least one active device thereon, connecting said active devices on said I/C chip structure through said first face of said I/C chip structure to said circuit board vias on said one face of said printed circuit board,
• providing a discrete decoupling capacitor structure comprising at least two interlaced conductive plates in dielectric material forming at least one capacitor;
• vias extending from each of said conductive plates through said dielectric material to connect each via to a connector on said second face of said I/C chip structure,
• said vias in said decoupling capacitor structure being configured and arranged such that the vias are parallel to each other, and each via connected to one conductive plate is located adjacent a via connected to another conductive plate, and
• connecting said vias in said decoupling capacitor to the vias in said I/C chip structure.